drm/i915/gvt: Fix mmio handler break on BXT/APL. (92010a97) · Commits · 戴 / test

- Remove dup mmio handler for BXT/APL. Otherwise mmio handler will fail to init. - Add engine GPR with F_CMD_ACCESS since BXT/APL will load them via LRI. Otherwise, guest will enter failsafe mode. V2: Use RCS/BCS GPR macros instead of offset. Revise commit message. V3: Use GEN8_RING_CS_GPR macros on ring base. Reviewed-by:

Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:

Colin Xu <colin.xu@intel.com> Signed-off-by:

Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20201016052913.209248-1-colin.xu@intel.com

drivers/gpu/drm/i915/gvt/handlers.c

+11 −1

Original line number	Diff line number	Diff line
		@@ -3168,7 +3168,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
		NULL, NULL);

		MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL \| D_CFL, F_CMD_ACCESS, NULL, NULL);
		MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
		MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);

		return 0;
		}
		@@ -3342,6 +3342,16 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
		MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
		MMIO_D(GEN6_GFXPAUSE, D_BXT);
		MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
		MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
		MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
		MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
		0, 0, D_BXT, NULL, NULL);
		MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
		0, 0, D_BXT, NULL, NULL);
		MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
		0, 0, D_BXT, NULL, NULL);
		MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
		0, 0, D_BXT, NULL, NULL);

		MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);

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