Commit 0c7c0c8e authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/gen12: Flush L3 



Flush TDL,L3 and EUs

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506144734.29297-3-mika.kuoppala@linux.intel.com
parent 32d7171e

drivers/gpu/drm/i915/gt/intel_lrc.c

+2 −0
Original line number Diff line number Diff line
@@ -4547,6 +4547,7 @@ static int gen12_emit_flush_render(struct i915_request *request, 
		u32 *cs;



		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;

		flags |= PIPE_CONTROL_FLUSH_L3;

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		/* Wa_1409600907:tgl */
@@ -4758,6 +4759,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 
				       PIPE_CONTROL0_HDC_PIPELINE_FLUSH,

				       PIPE_CONTROL_CS_STALL |

				       PIPE_CONTROL_TILE_CACHE_FLUSH |

				       PIPE_CONTROL_FLUSH_L3 |

				       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

				       PIPE_CONTROL_DEPTH_CACHE_FLUSH |

				       /* Wa_1409600907:tgl */

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