clk: tegra: Add PLL post divider table (0b6525ac) · Commits · 戴 / test

drivers/clk/tegra/clk-pll.c

+32 −6

Original line number	Diff line number	Diff line
		@@ -266,6 +266,7 @@ static int _calc_rate(struct clk_hw hw, struct tegra_clk_pll_freq_table cfg,
		unsigned long rate, unsigned long parent_rate)
		{
		struct tegra_clk_pll *pll = to_clk_pll(hw);
		struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
		unsigned long cfreq;
		u32 p_div = 0;

		@@ -299,7 +300,6 @@ static int _calc_rate(struct clk_hw hw, struct tegra_clk_pll_freq_table cfg,
		cfg->output_rate <<= 1)
		p_div++;

		cfg->p = p_div;
		cfg->m = parent_rate / cfreq;
		cfg->n = cfg->output_rate / cfreq;
		cfg->cpcon = OUT_OF_TABLE_CPCON;
		@@ -312,8 +312,19 @@ static int _calc_rate(struct clk_hw hw, struct tegra_clk_pll_freq_table cfg,
		return -EINVAL;
		}

		if (pll->flags & TEGRA_PLLU)
		cfg->p ^= 1;
		if (p_tohw) {
		p_div = 1 << p_div;
		while (p_tohw->pdiv) {
		if (p_div <= p_tohw->pdiv) {
		cfg->p = p_tohw->hw_val;
		break;
		}
		p_tohw++;
		}
		if (!p_tohw->pdiv)
		return -EINVAL;
		} else
		cfg->p = p_div;

		return 0;
		}
		@@ -460,8 +471,10 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
		{
		struct tegra_clk_pll *pll = to_clk_pll(hw);
		struct tegra_clk_pll_freq_table cfg;
		struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
		u32 val;
		u64 rate = parent_rate;
		int pdiv;

		val = pll_readl_base(pll);

		@@ -480,10 +493,23 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,

		_get_pll_mnp(pll, &cfg);

		if (pll->flags & TEGRA_PLLU)
		cfg.p ^= 1;
		if (p_tohw) {
		while (p_tohw->pdiv) {
		if (cfg.p == p_tohw->hw_val) {
		pdiv = p_tohw->pdiv;
		break;
		}
		p_tohw++;
		}

		if (!p_tohw->pdiv) {
		WARN_ON(1);
		pdiv = 1;
		}
		} else
		pdiv = 1 << cfg.p;

		cfg.m *= 1 << cfg.p;
		cfg.m *= pdiv;

		rate *= cfg.n;
		do_div(rate, cfg.m);

drivers/clk/tegra/clk-tegra20.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -441,6 +441,12 @@ static struct tegra_clk_pll_params pll_d_params = {
		.lock_delay = 1000,
		};

		static struct pdiv_map pllu_p[] = {
		{ .pdiv = 1, .hw_val = 1 },
		{ .pdiv = 2, .hw_val = 0 },
		{ .pdiv = 0, .hw_val = 0 },
		};

		static struct tegra_clk_pll_params pll_u_params = {
		.input_min = 2000000,
		.input_max = 40000000,
		@@ -453,6 +459,7 @@ static struct tegra_clk_pll_params pll_u_params = {
		.lock_bit_idx = PLL_BASE_LOCK,
		.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
		.lock_delay = 1000,
		.pdiv_tohw = pllu_p,
		};

		static struct tegra_clk_pll_params pll_x_params = {

drivers/clk/tegra/clk-tegra30.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -467,6 +467,12 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
		{ 0, 0, 0, 0, 0, 0 },
		};

		static struct pdiv_map pllu_p[] = {
		{ .pdiv = 1, .hw_val = 1 },
		{ .pdiv = 2, .hw_val = 0 },
		{ .pdiv = 0, .hw_val = 0 },
		};

		static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
		{ 12000000, 480000000, 960, 12, 0, 12},
		{ 13000000, 480000000, 960, 13, 0, 12},
		@@ -640,6 +646,7 @@ static struct tegra_clk_pll_params pll_u_params = {
		.lock_bit_idx = PLL_BASE_LOCK,
		.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
		.lock_delay = 1000,
		.pdiv_tohw = pllu_p,
		};

		static struct tegra_clk_pll_params pll_x_params = {

drivers/clk/tegra/clk.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -116,6 +116,17 @@ struct tegra_clk_pll_freq_table {
		u8 cpcon;
		};

		/**
		* struct pdiv_map - map post divider to hw value
		*
		* @pdiv: post divider
		* @hw_val: value to be written to the PLL hw
		*/
		struct pdiv_map {
		u8 pdiv;
		u8 hw_val;
		};

		/**
		* struct clk_pll_params - PLL parameters
		*
		@@ -146,6 +157,8 @@ struct tegra_clk_pll_params {
		u32 lock_bit_idx;
		u32 lock_enable_bit_idx;
		int lock_delay;
		int max_p;
		struct pdiv_map *pdiv_tohw;
		};

		/**

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