Commit 09d47620 authored by Anson Huang's avatar Anson Huang Committed by Stephen Boyd
Browse files

clk: imx6sl: add mmdc ipg clocks 



i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into
clock tree for clock management.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent aac7ff20

drivers/clk/imx/clk-imx6sl.c

+2 −0
Original line number Diff line number Diff line
@@ -386,6 +386,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SL_CLK_LCDIF_AXI]    = imx_clk_gate2("lcdif_axi",    "lcdif_axi_podf",    base + 0x74, 6);

	clks[IMX6SL_CLK_LCDIF_PIX]    = imx_clk_gate2("lcdif_pix",    "lcdif_pix_podf",    base + 0x74, 8);

	clks[IMX6SL_CLK_EPDC_PIX]     = imx_clk_gate2("epdc_pix",     "epdc_pix_podf",     base + 0x74, 10);

	clks[IMX6SL_CLK_MMDC_P0_IPG]  = imx_clk_gate2_flags("mmdc_p0_ipg",  "ipg",         base + 0x74,	24, CLK_IS_CRITICAL);

	clks[IMX6SL_CLK_MMDC_P1_IPG]  = imx_clk_gate2("mmdc_p1_ipg",  "ipg",	  	   base + 0x74,	26);

	clks[IMX6SL_CLK_OCRAM]        = imx_clk_gate2("ocram",        "ocram_podf",        base + 0x74, 28);

	clks[IMX6SL_CLK_PWM1]         = imx_clk_gate2("pwm1",         "perclk",            base + 0x78, 16);

	clks[IMX6SL_CLK_PWM2]         = imx_clk_gate2("pwm2",         "perclk",            base + 0x78, 18);

include/dt-bindings/clock/imx6sl-clock.h

+3 −1
Original line number Diff line number Diff line
@@ -175,6 +175,8 @@ 
#define IMX6SL_CLK_SSI2_IPG		162

#define IMX6SL_CLK_SSI3_IPG		163

#define IMX6SL_CLK_SPDIF_GCLK		164

#define IMX6SL_CLK_END			165

#define IMX6SL_CLK_MMDC_P0_IPG		165

#define IMX6SL_CLK_MMDC_P1_IPG		166

#define IMX6SL_CLK_END			167



#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

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