firmware: xilinx: Remove eemi ops for clock_getdivider (0667a8d1) · Commits · 戴 / test

drivers/clk/zynqmp/divider.c

+2 −4

Original line number	Diff line number	Diff line
		@@ -83,9 +83,8 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
		u32 div_type = divider->div_type;
		u32 div, value;
		int ret;
		const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

		ret = eemi_ops->clock_getdivider(clk_id, &div);
		ret = zynqmp_pm_clock_getdivider(clk_id, &div);

		if (ret)
		pr_warn_once("%s() get divider failed for %s, ret = %d\n",
		@@ -163,11 +162,10 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
		u32 div_type = divider->div_type;
		u32 bestdiv;
		int ret;
		const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

		/* if read only, just return current value */
		if (divider->flags & CLK_DIVIDER_READ_ONLY) {
		ret = eemi_ops->clock_getdivider(clk_id, &bestdiv);
		ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv);

		if (ret)
		pr_warn_once("%s() get divider failed for %s, ret = %d\n",

+1 −1

Original line number	Diff line number	Diff line
		@@ -141,7 +141,7 @@ static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
		int ret;
		const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

		ret = eemi_ops->clock_getdivider(clk_id, &fbdiv);
		ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
		if (ret)
		pr_warn_once("%s() get divider failed for %s, ret = %d\n",
		__func__, clk_name, ret);

+2 −2

Original line number	Diff line number	Diff line
		@@ -422,7 +422,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider);
		*
		* Return: Returns status, either success or error+reason
		*/
		static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
		int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
		{
		u32 ret_payload[PAYLOAD_ARG_CNT];
		int ret;
		@@ -433,6 +433,7 @@ static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)

		return ret;
		}
		EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getdivider);

		/**
		* zynqmp_pm_clock_setrate() - Set the clock rate for given id
		@@ -741,7 +742,6 @@ static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
		}

		static const struct zynqmp_eemi_ops eemi_ops = {
		.clock_getdivider = zynqmp_pm_clock_getdivider,
		.clock_setrate = zynqmp_pm_clock_setrate,
		.clock_getrate = zynqmp_pm_clock_getrate,
		.clock_setparent = zynqmp_pm_clock_setparent,

+5 −1

Original line number	Diff line number	Diff line
		@@ -296,7 +296,6 @@ struct zynqmp_pm_query_data {
		struct zynqmp_eemi_ops {
		int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
		int (fpga_get_status)(u32 value);
		int (clock_getdivider)(u32 clock_id, u32 divider);
		int (*clock_setrate)(u32 clock_id, u64 rate);
		int (clock_getrate)(u32 clock_id, u64 rate);
		int (*clock_setparent)(u32 clock_id, u32 parent_id);
		@@ -331,6 +330,7 @@ int zynqmp_pm_clock_enable(u32 clock_id);
		int zynqmp_pm_clock_disable(u32 clock_id);
		int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
		int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
		int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
		#else
		static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
		{
		@@ -365,6 +365,10 @@ static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
		{
		return -ENODEV;
		}
		static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
		{
		return -ENODEV;
		}
		#endif

		#endif /* __FIRMWARE_ZYNQMP_H__ */