firmware: xilinx: Remove eemi ops for clock_setdivider (fc9fb8fb) · Commits · 戴 / test

drivers/clk/zynqmp/divider.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -219,7 +219,6 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
		u32 div_type = divider->div_type;
		u32 value, div;
		int ret;
		const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

		value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
		if (div_type == TYPE_DIV1) {
		@@ -233,7 +232,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
		if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		div = __ffs(div);

		ret = eemi_ops->clock_setdivider(clk_id, div);
		ret = zynqmp_pm_clock_setdivider(clk_id, div);

		if (ret)
		pr_warn_once("%s() set divider failed for %s, ret = %d\n",

+2 −2

Original line number	Diff line number	Diff line
		@@ -187,7 +187,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		rate = parent_rate * m;
		frac = (parent_rate * f) / FRAC_DIV;

		ret = eemi_ops->clock_setdivider(clk_id, m);
		ret = zynqmp_pm_clock_setdivider(clk_id, m);
		if (ret == -EUSERS)
		WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
		clk_name);
		@@ -201,7 +201,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,

		fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
		fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
		ret = eemi_ops->clock_setdivider(clk_id, fbdiv);
		ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
		if (ret)
		pr_warn_once("%s() set divider failed for %s, ret = %d\n",
		__func__, clk_name, ret);

+2 −2

Original line number	Diff line number	Diff line
		@@ -405,11 +405,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate);
		*
		* Return: Returns status, either success or error+reason
		*/
		static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
		int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
		{
		return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider,
		0, 0, NULL);
		}
		EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider);

		/**
		* zynqmp_pm_clock_getdivider() - Get the clock divider for given id
		@@ -740,7 +741,6 @@ static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
		}

		static const struct zynqmp_eemi_ops eemi_ops = {
		.clock_setdivider = zynqmp_pm_clock_setdivider,
		.clock_getdivider = zynqmp_pm_clock_getdivider,
		.clock_setrate = zynqmp_pm_clock_setrate,
		.clock_getrate = zynqmp_pm_clock_getrate,

+5 −1

Original line number	Diff line number	Diff line
		@@ -296,7 +296,6 @@ struct zynqmp_pm_query_data {
		struct zynqmp_eemi_ops {
		int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
		int (fpga_get_status)(u32 value);
		int (*clock_setdivider)(u32 clock_id, u32 divider);
		int (clock_getdivider)(u32 clock_id, u32 divider);
		int (*clock_setrate)(u32 clock_id, u64 rate);
		int (clock_getrate)(u32 clock_id, u64 rate);
		@@ -331,6 +330,7 @@ int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
		int zynqmp_pm_clock_enable(u32 clock_id);
		int zynqmp_pm_clock_disable(u32 clock_id);
		int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
		int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
		#else
		static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
		{
		@@ -361,6 +361,10 @@ static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
		{
		return -ENODEV;
		}
		static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
		{
		return -ENODEV;
		}
		#endif

		#endif /* __FIRMWARE_ZYNQMP_H__ */