drm/vmwgfx: Sync virtual device headers for new feature (0651dfab) · Commits · 戴 / test

drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h

+120 −29

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 OR MIT */
		/**********************************************************
		* Copyright 1998-2015 VMware, Inc.
		* Copyright 1998-2020 VMware, Inc.
		*
		* Permission is hereby granted, free of charge, to any person
		* obtaining a copy of this software and associated documentation
		@@ -261,30 +261,23 @@ typedef enum {
		SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
		SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
		SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,

		/*
		* Reserve some IDs to be used for the SM5 shader types.
		*/
		SVGA_3D_CMD_DX_RESERVED1 = 1223,
		SVGA_3D_CMD_DX_RESERVED2 = 1224,
		SVGA_3D_CMD_DX_RESERVED3 = 1225,
		SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223,
		SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224,
		SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225,

		SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
		SVGA_3D_CMD_DX_MAX = 1227,

		SVGA_3D_CMD_SCREEN_COPY = 1227,

		/*
		* Reserve some IDs to be used for video.
		*/
		SVGA_3D_CMD_VIDEO_RESERVED1 = 1228,
		SVGA_3D_CMD_VIDEO_RESERVED2 = 1229,
		SVGA_3D_CMD_VIDEO_RESERVED3 = 1230,
		SVGA_3D_CMD_VIDEO_RESERVED4 = 1231,
		SVGA_3D_CMD_VIDEO_RESERVED5 = 1232,
		SVGA_3D_CMD_VIDEO_RESERVED6 = 1233,
		SVGA_3D_CMD_VIDEO_RESERVED7 = 1234,
		SVGA_3D_CMD_VIDEO_RESERVED8 = 1235,
		SVGA_3D_CMD_RESERVED1 = 1228,
		SVGA_3D_CMD_RESERVED2 = 1229,
		SVGA_3D_CMD_RESERVED3 = 1230,
		SVGA_3D_CMD_RESERVED4 = 1231,
		SVGA_3D_CMD_RESERVED5 = 1232,
		SVGA_3D_CMD_RESERVED6 = 1233,
		SVGA_3D_CMD_RESERVED7 = 1234,
		SVGA_3D_CMD_RESERVED8 = 1235,

		SVGA_3D_CMD_GROW_OTABLE = 1236,
		SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
		@@ -298,7 +291,46 @@ typedef enum {
		SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
		SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,

		SVGA_3D_CMD_MAX = 1245,
		SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245,
		SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246,
		SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247,
		SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248,
		SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249,
		SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250,

		SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251,
		SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252,
		SVGA_3D_CMD_DX_DISPATCH = 1253,
		SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254,

		SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255,
		SVGA_3D_CMD_HINT_ZERO_SURFACE = 1256,
		SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257,
		SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258,

		SVGA_3D_CMD_LOGICOPS_BITBLT = 1259,
		SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260,
		SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261,
		SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262,
		SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263,
		SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264,

		SVGA_3D_CMD_RESERVED2_1 = 1265,

		SVGA_3D_CMD_RESERVED2_2 = 1266,
		SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267,
		SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268,
		SVGA_3D_CMD_DX_SET_MIN_LOD = 1269,
		SVGA_3D_CMD_RESERVED2_3 = 1270,
		SVGA_3D_CMD_RESERVED2_4 = 1271,
		SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272,
		SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273,
		SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274,
		SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275,
		SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276,
		SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277,

		SVGA_3D_CMD_MAX = 1278,
		SVGA_3D_CMD_FUTURE_MAX = 3000
		} SVGAFifo3dCmdId;

		@@ -334,6 +366,7 @@ struct {
		uint32 sid;
		SVGA3dSurface1Flags surfaceFlags;
		SVGA3dSurfaceFormat format;

		/*
		* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
		* structures must have the same value of numMipLevels field.
		@@ -341,6 +374,7 @@ struct {
		* numMipLevels set to 0.
		*/
		SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];

		/*
		* Followed by an SVGA3dSize structure for each mip level in each face.
		*
		@@ -360,6 +394,7 @@ struct {
		uint32 sid;
		SVGA3dSurface1Flags surfaceFlags;
		SVGA3dSurfaceFormat format;

		/*
		* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
		* structures must have the same value of numMipLevels field.
		@@ -369,6 +404,7 @@ struct {
		SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
		uint32 multisampleCount;
		SVGA3dTextureFilter autogenFilter;

		/*
		* Followed by an SVGA3dSize structure for each mip level in each face.
		*
		@@ -512,6 +548,18 @@ struct {
		#include "vmware_pack_end.h"
		SVGA3dCmdWholeSurfaceCopy; /* SVGA_3D_CMD_WHOLE_SURFACE_COPY */

		typedef
		#include "vmware_pack_begin.h"
		struct {
		SVGA3dSurfaceImageId src;
		SVGA3dSurfaceImageId dest;
		SVGA3dBox boxSrc;
		SVGA3dBox boxDest;
		}
		#include "vmware_pack_end.h"
		SVGA3dCmdSurfaceStretchBltNonMSToMS;
		/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS */

		typedef
		#include "vmware_pack_begin.h"
		struct {
		@@ -555,6 +603,7 @@ struct {
		SVGAGuestImage guest;
		SVGA3dSurfaceImageId host;
		SVGA3dTransferType transfer;

		/*
		* Followed by variable number of SVGA3dCopyBox structures. For consistency
		* in all clipping logic and coordinate translation, we define the
		@@ -789,7 +838,7 @@ struct {

		uint32 indexBufferSid; /* Valid index buffer sid. */
		uint32 indexBufferOffset; /* Byte offset into the vertex buffer, almost */
		/* always 0 for DX9 guests, non-zero for OpenGL */
		/* always 0 for pre SM guests, non-zero for OpenGL */
		/* guests. We can't represent non-multiple of */
		/* stride offsets in D3D9Renderer... */
		uint8 indexBufferStride; /* Allowable values = 1, 2, or 4 */
		@@ -1228,6 +1277,7 @@ struct SVGA3dCmdLogicOpsBitBlt {
		SVGA3dSurfaceImageId src;
		SVGA3dSurfaceImageId dst;
		SVGA3dLogicOp logicOp;
		SVGA3dLogicOpRop3 logicOpRop3;
		/* Followed by variable number of SVGA3dCopyBox structures */
		}
		#include "vmware_pack_end.h"
		@@ -1247,7 +1297,8 @@ struct SVGA3dCmdLogicOpsTransBlt {
		uint32 color;
		uint32 flags;
		SVGA3dBox srcBox;
		SVGA3dBox dstBox;
		SVGA3dSignedBox dstBox;
		SVGA3dBox clipBox;
		}
		#include "vmware_pack_end.h"
		SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */
		@@ -1266,7 +1317,8 @@ struct SVGA3dCmdLogicOpsStretchBlt {
		uint16 mode;
		uint16 flags;
		SVGA3dBox srcBox;
		SVGA3dBox dstBox;
		SVGA3dSignedBox dstBox;
		SVGA3dBox clipBox;
		}
		#include "vmware_pack_end.h"
		SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
		@@ -1283,6 +1335,7 @@ struct SVGA3dCmdLogicOpsColorFill {
		SVGA3dSurfaceImageId dst;
		uint32 color;
		SVGA3dLogicOp logicOp;
		SVGA3dLogicOpRop3 logicOpRop3;
		/* Followed by variable number of SVGA3dRect structures. */
		}
		#include "vmware_pack_end.h"
		@@ -1302,7 +1355,8 @@ struct SVGA3dCmdLogicOpsAlphaBlend {
		uint32 alphaVal;
		uint32 flags;
		SVGA3dBox srcBox;
		SVGA3dBox dstBox;
		SVGA3dSignedBox dstBox;
		SVGA3dBox clipBox;
		}
		#include "vmware_pack_end.h"
		SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
		@@ -1365,8 +1419,9 @@ struct {
		SVGA3dSurface2Flags surface2Flags;
		uint8 multisamplePattern;
		uint8 qualityLevel;
		uint8 pad0[2];
		uint32 pad1[3];
		uint16 bufferByteStride;
		float minLOD;
		uint32 pad0[2];
		}
		#include "vmware_pack_end.h"
		SVGAOTableSurfaceEntry;
		@@ -1543,7 +1598,7 @@ typedef
		#include "vmware_pack_begin.h"
		struct {
		SVGAOTableType type;
		PPN baseAddress;
		PPN32 baseAddress;
		uint32 sizeInBytes;
		uint32 validSizeInBytes;
		SVGAMobFormat ptDepth;
		@@ -1599,7 +1654,7 @@ typedef
		struct SVGA3dCmdDefineGBMob {
		SVGAMobId mobid;
		SVGAMobFormat ptDepth;
		PPN base;
		PPN32 base;
		uint32 sizeInBytes;
		}
		#include "vmware_pack_end.h"
		@@ -1618,7 +1673,6 @@ struct SVGA3dCmdDestroyGBMob {
		#include "vmware_pack_end.h"
		SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */


		/*
		* Define a memory object (Mob) in the OTable with a PPN64 base.
		*/
		@@ -1718,6 +1772,27 @@ struct SVGA3dCmdDefineGBSurface_v3 {
		#include "vmware_pack_end.h"
		SVGA3dCmdDefineGBSurface_v3; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 */

		/*
		* Defines a guest-backed surface, adding buffer byte stride.
		*/
		typedef
		#include "vmware_pack_begin.h"
		struct SVGA3dCmdDefineGBSurface_v4 {
		uint32 sid;
		SVGA3dSurfaceAllFlags surfaceFlags;
		SVGA3dSurfaceFormat format;
		uint32 numMipLevels;
		uint32 multisampleCount;
		SVGA3dMSPattern multisamplePattern;
		SVGA3dMSQualityLevel qualityLevel;
		SVGA3dTextureFilter autogenFilter;
		SVGA3dSize size;
		uint32 arraySize;
		uint32 bufferByteStride;
		}
		#include "vmware_pack_end.h"
		SVGA3dCmdDefineGBSurface_v4; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 */

		/*
		* Destroy a guest-backed surface.
		*/
		@@ -2181,4 +2256,20 @@ SVGA3dCmdScreenCopy; /* SVGA_3D_CMD_SCREEN_COPY */
		#define SVGA_SCREEN_COPY_STATUS_SUCCESS 0x01
		#define SVGA_SCREEN_COPY_STATUS_INVALID 0xFFFFFFFF

		typedef
		#include "vmware_pack_begin.h"
		struct {
		uint32 sid;
		}
		#include "vmware_pack_end.h"
		SVGA3dCmdWriteZeroSurface; /* SVGA_3D_CMD_WRITE_ZERO_SURFACE */

		typedef
		#include "vmware_pack_begin.h"
		struct {
		uint32 sid;
		}
		#include "vmware_pack_end.h"
		SVGA3dCmdHintZeroSurface; /* SVGA_3D_CMD_HINT_ZERO_SURFACE */

		#endif /* _SVGA3D_CMD_H_ */

drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h

+408 −384

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h

+449 −17

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h

+32 −4

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 OR MIT */
		/**********************************************************
		* Copyright 2007-2015 VMware, Inc.
		* Copyright 2007-2019 VMware, Inc.
		*
		* Permission is hereby granted, free of charge, to any person
		* obtaining a copy of this software and associated documentation
		@@ -40,11 +40,25 @@
		#include "includeCheck.h"

		#define SVGA3D_NUM_CLIPPLANES 6
		#define SVGA3D_MAX_CONTEXT_IDS 256
		#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)

		/*
		* While there are separate bind-points for RenderTargetViews and
		* UnorderedAccessViews in a DXContext, there is in fact one shared
		* semantic space that the guest-driver can use on any given draw call.
		* So there are really only 8 slots that can be spilt up between them, with the
		* spliceIndex controlling where the UAV's sit in the collapsed array.
		*/
		#define SVGA3D_MAX_RENDER_TARGETS 8
		#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
		#define SVGA3D_MAX_UAVIEWS 8
		#define SVGA3D_MAX_CONTEXT_IDS 256
		#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
		#define SVGA3D_DX11_1_MAX_UAVIEWS 64

		/*
		* Maximum canonical size of a surface in host-backed mode (pre-GBObjects).
		*/
		#define SVGA3D_HB_MAX_SURFACE_SIZE MBYTES_2_BYTES(128)

		/*
		* Maximum ID a shader can be assigned on a given context.
		@@ -59,6 +73,8 @@
		#define SVGA3D_NUM_TEXTURE_UNITS 32
		#define SVGA3D_NUM_LIGHTS 8

		#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32

		/*
		* Maximum size in dwords of shader text the SVGA device will allow.
		* Currently 8 MB.
		@@ -67,6 +83,11 @@
		#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
		sizeof(uint32))

		/*
		* The maximum value of threadGroupCount in each dimension
		*/
		#define SVGA3D_MAX_SHADER_THREAD_GROUPS 65535

		#define SVGA3D_MAX_CLIP_PLANES 6

		/*
		@@ -85,7 +106,9 @@
		/*
		* Maximum number of array indexes in a GB surface (with DX enabled).
		*/
		#define SVGA3D_MAX_SURFACE_ARRAYSIZE 512
		#define SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE 512
		#define SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE 2048
		#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE

		/*
		* The maximum number of vertex arrays we're guaranteed to support in
		@@ -99,4 +122,9 @@
		*/
		#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32

		/*
		* The maximum number of samples that can be contained in a surface.
		*/
		#define SVGA3D_MAX_SAMPLES 8

		#endif /* _SVGA3D_LIMITS_H_ */

drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h

+56 −2

Original line number	Diff line number	Diff line
		@@ -131,6 +131,8 @@ enum svga3d_block_desc {
		SVGA3DBLOCKDESC_BC3 = 1 << 26,
		SVGA3DBLOCKDESC_BC4 = 1 << 27,
		SVGA3DBLOCKDESC_BC5 = 1 << 28,
		SVGA3DBLOCKDESC_BC6H = 1 << 29,
		SVGA3DBLOCKDESC_BC7 = 1 << 30,

		SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA \|
		SVGA3DBLOCKDESC_UINT \|
		@@ -290,6 +292,18 @@ enum svga3d_block_desc {
		SVGA3DBLOCKDESC_COMP_UNORM,
		SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 \|
		SVGA3DBLOCKDESC_COMP_SNORM,
		SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H \|
		SVGA3DBLOCKDESC_COMP_TYPELESS,
		SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H \|
		SVGA3DBLOCKDESC_COMPRESSED,
		SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H \|
		SVGA3DBLOCKDESC_COMPRESSED,
		SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 \|
		SVGA3DBLOCKDESC_COMP_TYPELESS,
		SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 \|
		SVGA3DBLOCKDESC_COMP_UNORM,
		SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM \|
		SVGA3DBLOCKDESC_SRGB,

		SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO \|
		SVGA3DBLOCKDESC_PLANAR_YUV \|
		@@ -494,7 +508,7 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
		{{8}, {8}, {8}, {0}},
		{{16}, {8}, {0}, {0}}},

		{SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_UVL,
		{SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE,
		{1, 1, 1}, 3, 3,
		{{8}, {8}, {8}, {0}},
		{{16}, {8}, {0}, {0}}},
		@@ -604,7 +618,7 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
		{{0}, {0}, {48}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
		{SVGA3D_FORMAT_DEAD2, SVGA3DBLOCKDESC_NONE,
		{1, 1, 1}, 4, 4,
		{{8}, {8}, {8}, {8}},
		{{0}, {8}, {16}, {24}}},
		@@ -1103,6 +1117,46 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
		{4, 4, 1}, 16, 16,
		{{0}, {0}, {128}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
		{1, 1, 1}, 2, 2,
		{{4}, {4}, {4}, {4}},
		{{0}, {4}, {8}, {12}}},

		{SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS,
		{4, 4, 1}, 16, 16,
		{{0}, {0}, {128}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16,
		{4, 4, 1}, 16, 16,
		{{0}, {0}, {128}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16,
		{4, 4, 1}, 16, 16,
		{{0}, {0}, {128}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS,
		{4, 4, 1}, 16, 16,
		{{0}, {0}, {128}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM,
		{4, 4, 1}, 16, 16,
		{{0}, {0}, {128}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB,
		{4, 4, 1}, 16, 16,
		{{0}, {0}, {128}, {0}},
		{{0}, {0}, {0}, {0}}},

		{SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
		{1, 1, 1}, 4, 4,
		{{8}, {8}, {8}, {8}},
		{{0}, {8}, {16}, {24}}},
		};

		static inline u32 clamped_umul32(u32 a, u32 b)

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