drm/vmwgfx: Use enum to represent graphics context capabilities (878c6ecd) · Commits · 戴 / test

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -731,7 +731,7 @@ static int vmw_context_define(struct drm_device dev, void data,
		};
		int ret;

		if (!dev_priv->has_dx && dx) {
		if (!has_sm4_context(dev_priv) && dx) {
		VMW_DEBUG_USER("DX contexts not supported by device.\n");
		return -EINVAL;
		}

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

+17 −17

Original line number	Diff line number	Diff line
		@@ -449,7 +449,7 @@ static int vmw_request_device(struct vmw_private *dev_priv)
		dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
		if (IS_ERR(dev_priv->cman)) {
		dev_priv->cman = NULL;
		dev_priv->has_dx = false;
		dev_priv->sm_type = VMW_SM_LEGACY;
		}

		ret = vmw_request_device_late(dev_priv);
		@@ -886,11 +886,22 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
		if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
		spin_lock(&dev_priv->cap_lock);
		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
		dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
		if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
		dev_priv->sm_type = VMW_SM_4;
		spin_unlock(&dev_priv->cap_lock);
		}

		vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);

		/* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
		if (has_sm4_context(dev_priv) &&
		(dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41);

		if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
		dev_priv->sm_type = VMW_SM_4_1;
		}

		ret = vmw_kms_init(dev_priv);
		if (unlikely(ret != 0))
		goto out_no_kms;
		@@ -900,23 +911,12 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
		if (ret)
		goto out_no_fifo;

		if (dev_priv->has_dx) {
		/*
		* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1
		* support
		*/
		if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) {
		vmw_write(dev_priv, SVGA_REG_DEV_CAP,
		SVGA3D_DEVCAP_SM41);
		dev_priv->has_sm4_1 = vmw_read(dev_priv,
		SVGA_REG_DEV_CAP);
		}
		}

		DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
		DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
		? "yes." : "no.");
		DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no.");
		if (dev_priv->sm_type == VMW_SM_4_1)
		DRM_INFO("SM4_1 support available.\n");
		if (dev_priv->sm_type == VMW_SM_4)
		DRM_INFO("SM4 support available.\n");

		snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
		VMWGFX_REPO, VMWGFX_GIT_VERSION);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

+38 −2

Original line number	Diff line number	Diff line
		@@ -441,6 +441,20 @@ enum {
		VMW_IRQTHREAD_MAX
		};

		/**
		* enum vmw_sm_type - Graphics context capability supported by device.
		* @VMW_SM_LEGACY: Pre DX context.
		* @VMW_SM_4: Context support upto SM4.
		* @VMW_SM_4_1: Context support upto SM4_1.
		* @VMW_SM_MAX: Should be the last.
		*/
		enum vmw_sm_type {
		VMW_SM_LEGACY = 0,
		VMW_SM_4,
		VMW_SM_4_1,
		VMW_SM_MAX
		};

		struct vmw_private {
		struct ttm_bo_device bdev;

		@@ -475,9 +489,9 @@ struct vmw_private {
		bool has_mob;
		spinlock_t hw_lock;
		spinlock_t cap_lock;
		bool has_dx;
		bool assume_16bpp;
		bool has_sm4_1;

		enum vmw_sm_type sm_type;

		/*
		* Framebuffer info.
		@@ -648,6 +662,28 @@ static inline uint32_t vmw_read(struct vmw_private *dev_priv,
		return val;
		}

		/**
		* has_sm4_context - Does the device support SM4 context.
		* @dev_priv: Device private.
		*
		* Return: Bool value if device support SM4 context or not.
		*/
		static inline bool has_sm4_context(const struct vmw_private *dev_priv)
		{
		return (dev_priv->sm_type >= VMW_SM_4);
		}

		/**
		* has_sm4_1_context - Does the device support SM4_1 context.
		* @dev_priv: Device private.
		*
		* Return: Bool value if device support SM4_1 context or not.
		*/
		static inline bool has_sm4_1_context(const struct vmw_private *dev_priv)
		{
		return (dev_priv->sm_type >= VMW_SM_4_1);
		}

		extern void vmw_svga_enable(struct vmw_private *dev_priv);
		extern void vmw_svga_disable(struct vmw_private *dev_priv);

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -461,7 +461,8 @@ static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
		u32 i;

		/* Add all cotables to the validation list. */
		if (dev_priv->has_dx && vmw_res_type(ctx) == vmw_res_dx_context) {
		if (has_sm4_context(dev_priv) &&
		vmw_res_type(ctx) == vmw_res_dx_context) {
		for (i = 0; i < SVGA_COTABLE_DX10_MAX; ++i) {
		res = vmw_context_cotable(ctx, i);
		if (IS_ERR(res))
		@@ -489,7 +490,8 @@ static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
		break;
		}

		if (dev_priv->has_dx && vmw_res_type(ctx) == vmw_res_dx_context) {
		if (has_sm4_context(dev_priv) &&
		vmw_res_type(ctx) == vmw_res_dx_context) {
		struct vmw_buffer_object *dx_query_mob;

		dx_query_mob = vmw_context_get_dx_query_mob(ctx);

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -114,10 +114,10 @@ int vmw_getparam_ioctl(struct drm_device dev, void data,
		(dev_priv->active_display_unit == vmw_du_screen_target);
		break;
		case DRM_VMW_PARAM_DX:
		param->value = dev_priv->has_dx;
		param->value = has_sm4_context(dev_priv);
		break;
		case DRM_VMW_PARAM_SM4_1:
		param->value = dev_priv->has_sm4_1;
		param->value = has_sm4_1_context(dev_priv);
		break;
		default:
		return -EINVAL;

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