Commit 04b68467 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
Browse files

staging: comedi: ni_stc.h: tidy up Second_IRQ_B_Enable_Register and bits 



Rename the CamelCase. The bit defines are identical to NISTC_INTB_ENA_REG.
Reuse them.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4c9c1d2c

drivers/staging/comedi/drivers/ni_mio_common.c

+3 −3
Original line number Diff line number Diff line
@@ -369,7 +369,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = { 
	[NISTC_INTA_ENA_REG]		= { 0x192, 2 },

	[NISTC_INTA2_ENA_REG]		= { 0, 0 }, /* E-Series only */

	[NISTC_INTB_ENA_REG]		= { 0x196, 2 },

	[Second_IRQ_B_Enable_Register]	= { 0, 0 }, /* E-Series only */

	[NISTC_INTB2_ENA_REG]		= { 0, 0 }, /* E-Series only */

	[AI_Personal_Register]		= { 0x19a, 2 },

	[AO_Personal_Register]		= { 0x19c, 2 },

	[RTSI_Trig_A_Output_Register]	= { 0x19e, 2 },
@@ -822,9 +822,9 @@ static void ni_e_series_enable_second_irq(struct comedi_device *dev, 
		if (enable)

			val = NISTC_INTA_ENA_G0_GATE;

	} else {

		reg = Second_IRQ_B_Enable_Register;

		reg = NISTC_INTB2_ENA_REG;

		if (enable)

			val = G1_Gate_Second_Irq_Enable;

			val = NISTC_INTB_ENA_G1_GATE;

	}

	ni_stc_writew(dev, val, reg);

}

drivers/staging/comedi/drivers/ni_stc.h

+1 −16
Original line number Diff line number Diff line
@@ -405,6 +405,7 @@ 
					 NISTC_INTA_ENA_AI_SC_TC)



#define NISTC_INTB_ENA_REG		75

#define NISTC_INTB2_ENA_REG		76

#define NISTC_INTB_ENA_PASSTHRU1	BIT(11)

#define NISTC_INTB_ENA_G1_GATE		BIT(10)

#define NISTC_INTB_ENA_G1_TC		BIT(9)
@@ -476,22 +477,6 @@ enum Joint_Status_2_Bits { 
#define AO_BC_Save_Registers		18

#define AO_UC_Save_Registers		20



#define Second_IRQ_B_Enable_Register	76

enum Second_IRQ_B_Enable_Bits {

	AO_BC_TC_Second_Irq_Enable = _bit0,

	AO_START1_Second_Irq_Enable = _bit1,

	AO_UPDATE_Second_Irq_Enable = _bit2,

	AO_START_Second_Irq_Enable = _bit3,

	AO_STOP_Second_Irq_Enable = _bit4,

	AO_Error_Second_Irq_Enable = _bit5,

	AO_UC_TC_Second_Irq_Enable = _bit6,

	AO_UI2_TC_Second_Irq_Enable = _bit7,

	AO_FIFO_Second_Irq_Enable = _bit8,

	G1_TC_Second_Irq_Enable = _bit9,

	G1_Gate_Second_Irq_Enable = _bit10,

	Pass_Thru_1_Second_Irq_Enable = _bit11

};



#define AI_Personal_Register		77

#define AI_SHIFTIN_Pulse_Width			_bit15

#define AI_EOC_Polarity				_bit14

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