Commit 4c9c1d2c authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
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staging: comedi: ni_stc.h: tidy up Interrupt_B_Enable_Register and bits 



Rename the CamelCase. Use the BIT() macro to define the bits.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d84e9c34

drivers/staging/comedi/drivers/ni_mio_common.c

+15 −15
Original line number Diff line number Diff line
@@ -368,7 +368,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = { 
	[NISTC_RESET_REG]		= { 0x190, 2 },

	[NISTC_INTA_ENA_REG]		= { 0x192, 2 },

	[NISTC_INTA2_ENA_REG]		= { 0, 0 }, /* E-Series only */

	[Interrupt_B_Enable_Register]	= { 0x196, 2 },

	[NISTC_INTB_ENA_REG]		= { 0x196, 2 },

	[Second_IRQ_B_Enable_Register]	= { 0, 0 }, /* E-Series only */

	[AI_Personal_Register]		= { 0x19a, 2 },

	[AO_Personal_Register]		= { 0x19c, 2 },
@@ -536,7 +536,7 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, 
		devpriv->int_a_enable_reg |= bit_values & bit_mask;

		ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);

		break;

	case Interrupt_B_Enable_Register:

	case NISTC_INTB_ENA_REG:

		devpriv->int_b_enable_reg &= ~bit_mask;

		devpriv->int_b_enable_reg |= bit_values & bit_mask;

		ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
@@ -1490,9 +1490,9 @@ static void handle_b_interrupt(struct comedi_device *dev, 
		ret = ni_ao_fifo_half_empty(dev, s);

		if (!ret) {

			dev_err(dev->class_dev, "AO buffer underrun\n");

			ni_set_bits(dev, Interrupt_B_Enable_Register,

				    AO_FIFO_Interrupt_Enable |

				    AO_Error_Interrupt_Enable, 0);

			ni_set_bits(dev, NISTC_INTB_ENA_REG,

				    NISTC_INTB_ENA_AO_FIFO |

				    NISTC_INTB_ENA_AO_ERR, 0);

			s->async->events |= COMEDI_CB_OVERFLOW;

		}

	}
@@ -2831,9 +2831,9 @@ static int ni_ao_inttrig(struct comedi_device *dev, 
	   multiple times) */

	s->async->inttrig = NULL;



	ni_set_bits(dev, Interrupt_B_Enable_Register,

		    AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);

	interrupt_b_bits = AO_Error_Interrupt_Enable;

	ni_set_bits(dev, NISTC_INTB_ENA_REG,

		    NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);

	interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;

#ifdef PCIDMA

	ni_stc_writew(dev, 1, DAC_FIFO_Clear);

	if (devpriv->is_6xxx)
@@ -2849,7 +2849,7 @@ static int ni_ao_inttrig(struct comedi_device *dev, 
	if (ret == 0)

		return -EPIPE;



	interrupt_b_bits |= AO_FIFO_Interrupt_Enable;

	interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;

#endif



	ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
@@ -2873,7 +2873,7 @@ static int ni_ao_inttrig(struct comedi_device *dev, 
	 */

	ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);



	ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);

	ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);



	ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |

			   NISTC_AO_CMD1_UC_ARM |
@@ -3092,8 +3092,8 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	if (cmd->stop_src == TRIG_COUNT) {

		ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,

			      NISTC_INTB_ACK_REG);

		ni_set_bits(dev, Interrupt_B_Enable_Register,

			    AO_BC_TC_Interrupt_Enable, 1);

		ni_set_bits(dev, NISTC_INTB_ENA_REG,

			    NISTC_INTB_ENA_AO_BC_TC, 1);

	}



	s->async->inttrig = ni_ao_inttrig;
@@ -3192,7 +3192,7 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) 


	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);

	ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);

	ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);

	ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);

	ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);

	ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);

	ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
@@ -3742,7 +3742,7 @@ static const struct mio_regmap ni_gpct_to_stc_regmap[] = { 
	[NITIO_G0_STATUS]	= { AI_Status_1_Register, 2 },

	[NITIO_G1_STATUS]	= { AO_Status_1_Register, 2 },

	[NITIO_G0_INT_ENA]	= { NISTC_INTA_ENA_REG, 2 },

	[NITIO_G1_INT_ENA]	= { Interrupt_B_Enable_Register, 2 },

	[NITIO_G1_INT_ENA]	= { NISTC_INTB_ENA_REG, 2 },

};



static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
@@ -3769,7 +3769,7 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 
	static const unsigned gpct_interrupt_a_enable_mask =

	    NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;

	static const unsigned gpct_interrupt_b_enable_mask =

	    G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;

	    NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;



	if (stc_register == 0)

		return;

drivers/staging/comedi/drivers/ni_stc.h

+14 −14
Original line number Diff line number Diff line
@@ -404,6 +404,20 @@ 
					 NISTC_INTA_ENA_AI_START1 |	\

					 NISTC_INTA_ENA_AI_SC_TC)



#define NISTC_INTB_ENA_REG		75

#define NISTC_INTB_ENA_PASSTHRU1	BIT(11)

#define NISTC_INTB_ENA_G1_GATE		BIT(10)

#define NISTC_INTB_ENA_G1_TC		BIT(9)

#define NISTC_INTB_ENA_AO_FIFO		BIT(8)

#define NISTC_INTB_ENA_AO_UI2_TC	BIT(7)

#define NISTC_INTB_ENA_AO_UC_TC		BIT(6)

#define NISTC_INTB_ENA_AO_ERR		BIT(5)

#define NISTC_INTB_ENA_AO_STOP		BIT(4)

#define NISTC_INTB_ENA_AO_START		BIT(3)

#define NISTC_INTB_ENA_AO_UPDATE	BIT(2)

#define NISTC_INTB_ENA_AO_START1	BIT(1)

#define NISTC_INTB_ENA_AO_BC_TC		BIT(0)



#define AI_Status_1_Register		2

#define Interrupt_A_St				0x8000

#define AI_FIFO_Full_St				0x4000
@@ -462,20 +476,6 @@ enum Joint_Status_2_Bits { 
#define AO_BC_Save_Registers		18

#define AO_UC_Save_Registers		20



#define Interrupt_B_Enable_Register	75

#define Pass_Thru_1_Interrupt_Enable		_bit11

#define G1_Gate_Interrupt_Enable		_bit10

#define G1_TC_Interrupt_Enable			_bit9

#define AO_FIFO_Interrupt_Enable		_bit8

#define AO_UI2_TC_Interrupt_Enable		_bit7

#define AO_UC_TC_Interrupt_Enable		_bit6

#define AO_Error_Interrupt_Enable		_bit5

#define AO_STOP_Interrupt_Enable		_bit4

#define AO_START_Interrupt_Enable		_bit3

#define AO_UPDATE_Interrupt_Enable		_bit2

#define AO_START1_Interrupt_Enable		_bit1

#define AO_BC_TC_Interrupt_Enable		_bit0



#define Second_IRQ_B_Enable_Register	76

enum Second_IRQ_B_Enable_Bits {

	AO_BC_TC_Second_Irq_Enable = _bit0,

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