arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register (011e5f5b) · Commits · 戴 / test

Enable MPAM and SEL2 features bits in ID_AA64PFR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by:

Will Deacon <will@kernel.org> Signed-off-by:

Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-11-git-send-email-anshuman.khandual@arm.com [will: Make SEL2 a NONSTRICT feature per Suzuki] Signed-off-by:

Will Deacon <will@kernel.org>

arch/arm64/include/asm/sysreg.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -645,6 +645,8 @@
		#define ID_AA64PFR0_CSV2_SHIFT 56
		#define ID_AA64PFR0_DIT_SHIFT 48
		#define ID_AA64PFR0_AMU_SHIFT 44
		#define ID_AA64PFR0_MPAM_SHIFT 40
		#define ID_AA64PFR0_SEL2_SHIFT 36
		#define ID_AA64PFR0_SVE_SHIFT 32
		#define ID_AA64PFR0_RAS_SHIFT 28
		#define ID_AA64PFR0_GIC_SHIFT 24

arch/arm64/kernel/cpufeature.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -222,6 +222,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
		FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),

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