Commit 00c543f6 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'aspeed-5.11-soc' of... 

Merge tag 'aspeed-5.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/drivers

ASPEED soc driver updates for 5.11

New drivers:

 - SoC info driver to expose revision information

New features:

 - AST2600 support for the LPC control driver. This includes
   setting the LPC2AHB bridge up in a backwards compatible manner.

Cleanups:

 - LPC control
 - Kconfig
 - Bindings updates for AST2600 strings

* tag 'aspeed-5.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
  soc: aspeed: Enable drivers with ARCH_ASPEED
  soc: aspeed: Fix a reference leak in aspeed_socinfo_init()
  soc: aspeed: remove unneeded semicolon
  soc: aspeed-lpc-ctrl: Fix driver name
  soc: aspeed-lpc-ctrl: Fix whitespace
  soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600
  soc: aspeed-lpc-ctrl: Fail probe of lpc-ctrl if reserved memory is not aligned
  soc: aspeed: lpc: Add AST2600 compatible strings
  dt-bindings: aspeed-lpc: Add AST2600 compatible strings
  ARM: dts: aspeed: Add silicon id node
  soc: aspeed: Add soc info driver
  dt-bindings: aspeed: Add silicon id node to SCU
  soc: aspeed: Improve kconfig

Link: https://lore.kernel.org/r/CACPK8Xe=9ezhyWRMqVOEQr7SU1YoYfVBGGdGzjmE4SiBr--vJQ@mail.gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents bbecede4 4da595dd

Documentation/devicetree/bindings/mfd/aspeed-lpc.txt

+7 −1
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ Required properties 
- compatible:	One of:

		"aspeed,ast2400-lpc", "simple-mfd"

		"aspeed,ast2500-lpc", "simple-mfd"

		"aspeed,ast2600-lpc", "simple-mfd"



- reg:		contains the physical address and length values of the Aspeed

                LPC memory region.
@@ -64,6 +65,7 @@ BMC Node 
- compatible:	One of:

		"aspeed,ast2400-lpc-bmc"

		"aspeed,ast2500-lpc-bmc"

		"aspeed,ast2600-lpc-bmc"



- reg:		contains the physical address and length values of the

                H8S/2168-compatible LPC controller memory region
@@ -74,6 +76,7 @@ Host Node 
- compatible:   One of:

		"aspeed,ast2400-lpc-host", "simple-mfd", "syscon"

		"aspeed,ast2500-lpc-host", "simple-mfd", "syscon"

		"aspeed,ast2600-lpc-host", "simple-mfd", "syscon"



- reg:		contains the address and length values of the host-related

                register space for the Aspeed LPC controller
@@ -128,6 +131,7 @@ Required properties: 
- compatible:	One of:

		"aspeed,ast2400-lpc-ctrl";

		"aspeed,ast2500-lpc-ctrl";

		"aspeed,ast2600-lpc-ctrl";



- reg:		contains offset/length values of the host interface controller

		memory regions
@@ -168,6 +172,7 @@ Required properties: 
- compatible:	One of:

		"aspeed,ast2400-lhc";

		"aspeed,ast2500-lhc";

		"aspeed,ast2600-lhc";



- reg:		contains offset/length values of the LHC memory regions. In the

		AST2400 and AST2500 there are two regions.
@@ -187,7 +192,8 @@ state of the LPC bus. Some systems may chose to modify this configuration. 


Required properties:



 - compatible:		"aspeed,ast2500-lpc-reset" or

 - compatible:		"aspeed,ast2600-lpc-reset" or

			"aspeed,ast2500-lpc-reset"

			"aspeed,ast2400-lpc-reset"

 - reg:			offset and length of the IP in the LHC memory region

 - #reset-controller	indicates the number of reset cells expected

Documentation/devicetree/bindings/mfd/aspeed-scu.txt

+26 −0
Original line number Diff line number Diff line
@@ -20,3 +20,29 @@ syscon: syscon@1e6e2000 { 
	#clock-cells = <1>;

	#reset-cells = <1>;

};



Silicon ID

-----------------



Families have unique hardware silicon identifiers within the SoC.



Required properties:



 - compatible:		"aspeed,silicon-id" or:

			"aspeed,ast2400-silicon-id" or

			"aspeed,ast2500-silicon-id" or

			"aspeed,ast2600-silicon-id"



 - reg:			offset and length of the silicon id information

			optionally, a second offset and length describes the unique chip id



			The reg should be the unique silicon id register, and

			not backwards compatible one in eg. the 2600.



Example:





silicon-id@7c {

        compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";

        reg = <0x7c 0x4 0x150 0x8>;

};

arch/arm/boot/dts/aspeed-g4.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -192,6 +192,11 @@ 
					status = "disabled";

				};



				silicon-id@7c {

					compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id";

					reg = <0x7c 0x4>;

				};



				pinctrl: pinctrl@80 {

					reg = <0x80 0x18>, <0xa0 0x10>;

					compatible = "aspeed,ast2400-pinctrl";

arch/arm/boot/dts/aspeed-g5.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -239,6 +239,11 @@ 
					status = "disabled";

				};



				silicon-id@7c {

					compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";

					reg = <0x7c 0x4 0x150 0x8>;

				};



				pinctrl: pinctrl@80 {

					compatible = "aspeed,ast2500-pinctrl";

					reg = <0x80 0x18>, <0xa0 0x10>;

arch/arm/boot/dts/aspeed-g6.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -311,6 +311,11 @@ 
					compatible = "aspeed,ast2600-pinctrl";

				};



				silicon-id@14 {

					compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id";

					reg = <0x14 0x4 0x5b0 0x8>;

				};



				smp-memram@180 {

					compatible = "aspeed,ast2600-smpmem";

					reg = <0x180 0x40>;

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