Commit bbecede4 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.10-next-soc' of... 

Merge tag 'v5.10-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

power-domains:
- add support for new power domain driver.
- add support for mt8183 and mt8192

devapc:
- add support for the devapc device found on mt6779 to identify of
  malicious bus accesses from a controller to a device

mmsys:
- move DDP routing IDs into the driver

cmdq:
- drop timeout handler support as not usefull

scpsys:
- print warning on theoretical error

* tag 'v5.10-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (21 commits)
  soc: mediatek: mmsys: Use devm_platform_ioremap_resource()
  soc / drm: mediatek: Move DDP component defines into mtk-mmsys.h
  soc: mediatek: add mt6779 devapc driver
  dt-bindings: devapc: add bindings for mtk-devapc
  soc / drm: mediatek: cmdq: Remove timeout handler in helper function
  soc: mediatek: pm-domains: Add support for mt8192
  soc: mediatek: pm-domains: Add default power off flag
  soc: mediatek: pm-domains: Add support for mt8183
  soc: mediatek: pm-domains: Allow bus protection to ignore clear ack
  soc: mediatek: pm-domains: Add subsystem clocks
  soc: mediatek: pm-domains: Add extra sram control
  soc: mediatek: pm-domains: Add SMI block as bus protection block
  soc: mediatek: pm_domains: Make bus protection generic
  soc: mediatek: pm-domains: Add bus protection protocol
  soc: mediatek: Add MediaTek SCPSYS power domains
  dt-bindings: power: Add MT8192 power domains
  dt-bindings: power: Add MT8183 power domains
  dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains controller
  mfd: syscon: Add syscon_regmap_lookup_by_phandle_optional() function.
  MAINTAINERS: change mediatek wiki page
  ...

Link: https://lore.kernel.org/r/b03fe343-e183-c6f3-f2dc-4c58aae3146b@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e9ab9c33 cc657602

Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

0 → 100644
+293 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mediatek Power Domains Controller



maintainers:

  - Weiyi Lu <weiyi.lu@mediatek.com>

  - Matthias Brugger <mbrugger@suse.com>



description: |

  Mediatek processors include support for multiple power domains which can be

  powered up/down by software based on different application scenes to save power.



  IP cores belonging to a power domain should contain a 'power-domains'

  property that is a phandle for SCPSYS node representing the domain.



properties:

  $nodename:

    const: power-controller



  compatible:

    enum:

      - mediatek,mt8173-power-controller

      - mediatek,mt8183-power-controller

      - mediatek,mt8192-power-controller



  '#power-domain-cells':

    const: 1



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



patternProperties:

  "^power-domain@[0-9a-f]+$":

    type: object

    description: |

      Represents the power domains within the power controller node as documented

      in Documentation/devicetree/bindings/power/power-domain.yaml.



    properties:



      '#power-domain-cells':

        description:

          Must be 0 for nodes representing a single PM domain and 1 for nodes

          providing multiple PM domains.



      '#address-cells':

        const: 1



      '#size-cells':

        const: 0



      reg:

        description: |

          Power domain index. Valid values are defined in:

              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.

              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.

              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.

        maxItems: 1



      clocks:

        description: |

          A number of phandles to clocks that need to be enabled during domain

          power-up sequencing.



      clock-names:

        description: |

          List of names of clocks, in order to match the power-up sequencing

          for each power domain we need to group the clocks by name. BASIC

          clocks need to be enabled before enabling the corresponding power

          domain, and should not have a '-' in their name (i.e mm, mfg, venc).

          SUSBYS clocks need to be enabled before releasing the bus protection,

          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



          In order to follow properly the power-up sequencing, the clocks must

          be specified by order, adding first the BASIC clocks followed by the

          SUSBSYS clocks.



      mediatek,infracfg:

        $ref: /schemas/types.yaml#definitions/phandle

        description: phandle to the device containing the INFRACFG register range.



      mediatek,smi:

        $ref: /schemas/types.yaml#definitions/phandle

        description: phandle to the device containing the SMI register range.



    patternProperties:

      "^power-domain@[0-9a-f]+$":

        type: object

        description: |

          Represents a power domain child within a power domain parent node.



        properties:



          '#power-domain-cells':

            description:

              Must be 0 for nodes representing a single PM domain and 1 for nodes

              providing multiple PM domains.



          '#address-cells':

            const: 1



          '#size-cells':

            const: 0



          reg:

            maxItems: 1



          clocks:

            description: |

              A number of phandles to clocks that need to be enabled during domain

              power-up sequencing.



          clock-names:

            description: |

              List of names of clocks, in order to match the power-up sequencing

              for each power domain we need to group the clocks by name. BASIC

              clocks need to be enabled before enabling the corresponding power

              domain, and should not have a '-' in their name (i.e mm, mfg, venc).

              SUSBYS clocks need to be enabled before releasing the bus protection,

              and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



              In order to follow properly the power-up sequencing, the clocks must

              be specified by order, adding first the BASIC clocks followed by the

              SUSBSYS clocks.



          mediatek,infracfg:

            $ref: /schemas/types.yaml#definitions/phandle

            description: phandle to the device containing the INFRACFG register range.



          mediatek,smi:

            $ref: /schemas/types.yaml#definitions/phandle

            description: phandle to the device containing the SMI register range.



        patternProperties:

          "^power-domain@[0-9a-f]+$":

            type: object

            description: |

              Represents a power domain child within a power domain parent node.



            properties:



              '#power-domain-cells':

                description:

                  Must be 0 for nodes representing a single PM domain and 1 for nodes

                  providing multiple PM domains.



              '#address-cells':

                const: 1



              '#size-cells':

                const: 0



              reg:

                maxItems: 1



              clocks:

                description: |

                  A number of phandles to clocks that need to be enabled during domain

                  power-up sequencing.



              clock-names:

                description: |

                  List of names of clocks, in order to match the power-up sequencing

                  for each power domain we need to group the clocks by name. BASIC

                  clocks need to be enabled before enabling the corresponding power

                  domain, and should not have a '-' in their name (i.e mm, mfg, venc).

                  SUSBYS clocks need to be enabled before releasing the bus protection,

                  and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



                  In order to follow properly the power-up sequencing, the clocks must

                  be specified by order, adding first the BASIC clocks followed by the

                  SUSBSYS clocks.



              mediatek,infracfg:

                $ref: /schemas/types.yaml#definitions/phandle

                description: phandle to the device containing the INFRACFG register range.



              mediatek,smi:

                $ref: /schemas/types.yaml#definitions/phandle

                description: phandle to the device containing the SMI register range.



            required:

              - reg



            additionalProperties: false



        required:

          - reg



        additionalProperties: false



    required:

      - reg



    additionalProperties: false



required:

  - compatible



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8173-clk.h>

    #include <dt-bindings/power/mt8173-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        scpsys: syscon@10006000 {

            compatible = "syscon", "simple-mfd";

            reg = <0 0x10006000 0 0x1000>;



            spm: power-controller {

                compatible = "mediatek,mt8173-power-controller";

                #address-cells = <1>;

                #size-cells = <0>;

                #power-domain-cells = <1>;



                /* power domains of the SoC */

                power-domain@MT8173_POWER_DOMAIN_VDEC {

                    reg = <MT8173_POWER_DOMAIN_VDEC>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>;

                    clock-names = "mm";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_VENC {

                    reg = <MT8173_POWER_DOMAIN_VENC>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>,

                             <&topckgen CLK_TOP_VENC_SEL>;

                    clock-names = "mm", "venc";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_ISP {

                    reg = <MT8173_POWER_DOMAIN_ISP>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>;

                    clock-names = "mm";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_MM {

                    reg = <MT8173_POWER_DOMAIN_MM>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>;

                    clock-names = "mm";

                    #power-domain-cells = <0>;

                    mediatek,infracfg = <&infracfg>;

                };

                power-domain@MT8173_POWER_DOMAIN_VENC_LT {

                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>,

                             <&topckgen CLK_TOP_VENC_LT_SEL>;

                    clock-names = "mm", "venclt";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_AUDIO {

                    reg = <MT8173_POWER_DOMAIN_AUDIO>;

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_USB {

                    reg = <MT8173_POWER_DOMAIN_USB>;

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {

                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;

                    clocks = <&clk26m>;

                    clock-names = "mfg";

                    #address-cells = <1>;

                    #size-cells = <0>;

                    #power-domain-cells = <1>;



                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {

                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;

                        #address-cells = <1>;

                        #size-cells = <0>;

                        #power-domain-cells = <1>;



                        power-domain@MT8173_POWER_DOMAIN_MFG {

                            reg = <MT8173_POWER_DOMAIN_MFG>;

                            #power-domain-cells = <0>;

                            mediatek,infracfg = <&infracfg>;

                        };

                    };

                };

            };

        };

    };

Documentation/devicetree/bindings/soc/mediatek/devapc.yaml

0 → 100644
+58 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# # Copyright 2020 MediaTek Inc.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/soc/mediatek/devapc.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek Device Access Permission Control driver



description: |

  MediaTek bus fabric provides TrustZone security support and data

  protection to prevent slaves from being accessed by unexpected masters.

  The security violation is logged and sent to the processor for further

  analysis and countermeasures.



maintainers:

  - Neal Liu <neal.liu@mediatek.com>



properties:

  compatible:

    enum:

      - mediatek,mt6779-devapc



  reg:

    description: The base address of devapc register bank

    maxItems: 1



  interrupts:

    description: A single interrupt specifier

    maxItems: 1



  clocks:

    description: Contains module clock source and clock names

    maxItems: 1



  clock-names:

    description: Names of the clocks list in clocks property

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/mt6779-clk.h>



    devapc: devapc@10207000 {

      compatible = "mediatek,mt6779-devapc";

      reg = <0x10207000 0x1000>;

      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;

      clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;

      clock-names = "devapc-infra-clock";

    };

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -2067,7 +2067,7 @@ M: Matthias Brugger <matthias.bgg@gmail.com> 
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

W:	https://mtk.bcnfs.org/

W:	https://mtk.wiki.kernel.org/

C:	irc://chat.freenode.net/linux-mediatek

F:	arch/arm/boot/dts/mt6*

F:	arch/arm/boot/dts/mt7*

drivers/gpu/drm/mediatek/mtk_drm_crtc.c

+1 −2
Original line number Diff line number Diff line
@@ -824,8 +824,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	mtk_crtc->cmdq_client =

			cmdq_mbox_create(mtk_crtc->mmsys_dev,

					 drm_crtc_index(&mtk_crtc->base),

					 2000);

					 drm_crtc_index(&mtk_crtc->base));

	if (IS_ERR(mtk_crtc->cmdq_client)) {

		dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",

			drm_crtc_index(&mtk_crtc->base));

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h

+1 −33
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#define MTK_DRM_DDP_COMP_H



#include <linux/io.h>

#include <linux/soc/mediatek/mtk-mmsys.h>



struct device;

struct device_node;
@@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { 
	MTK_DDP_COMP_TYPE_MAX,

};



enum mtk_ddp_comp_id {

	DDP_COMPONENT_AAL0,

	DDP_COMPONENT_AAL1,

	DDP_COMPONENT_BLS,

	DDP_COMPONENT_CCORR,

	DDP_COMPONENT_COLOR0,

	DDP_COMPONENT_COLOR1,

	DDP_COMPONENT_DITHER,

	DDP_COMPONENT_DPI0,

	DDP_COMPONENT_DPI1,

	DDP_COMPONENT_DSI0,

	DDP_COMPONENT_DSI1,

	DDP_COMPONENT_DSI2,

	DDP_COMPONENT_DSI3,

	DDP_COMPONENT_GAMMA,

	DDP_COMPONENT_OD0,

	DDP_COMPONENT_OD1,

	DDP_COMPONENT_OVL0,

	DDP_COMPONENT_OVL_2L0,

	DDP_COMPONENT_OVL_2L1,

	DDP_COMPONENT_OVL1,

	DDP_COMPONENT_PWM0,

	DDP_COMPONENT_PWM1,

	DDP_COMPONENT_PWM2,

	DDP_COMPONENT_RDMA0,

	DDP_COMPONENT_RDMA1,

	DDP_COMPONENT_RDMA2,

	DDP_COMPONENT_UFOE,

	DDP_COMPONENT_WDMA0,

	DDP_COMPONENT_WDMA1,

	DDP_COMPONENT_ID_MAX,

};



struct mtk_ddp_comp;

struct cmdq_pkt;

struct mtk_ddp_comp_funcs {

CRA Git | Maintained and supported by SUSTech CRA and CCSE