Commit fe5c11db authored by Andy Ross's avatar Andy Ross Committed by Benjamin Cabé
Browse files

boards/mediatek: Add mt8196_adsp 



Add Zephyr support for the Audio DSP on the MT8196 SOC.  This is a
very similar device to previous designs.  Most of this patch is just
DTS.

The biggest delta is the more complicated second level interrupt
controller, though it is still able to be represented using some
vaguely clever DTS config over the older intc_mtk_adsp driver.

Also the memory layout is slightly different, requiring a little
indirection to set the initial boot stack address and log output
buffer.  And the timer "irq_ack" register bits moved.

Signed-off-by: default avatarAndy Ross <andyross@google.com>
parent e35de00f

boards/mediatek/mt8196/Kconfig.mt8196

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# Copyright 2024 The ChromiumOS Authors

# SPDX-License-Identifier: Apache-2.0



config BOARD_MT8196

	select SOC_MT8196

boards/mediatek/mt8196/board.yml

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boards:

  - name: mt8196

    vendor: mediatek

    socs:

      - name: mt8196

boards/mediatek/mt8196/mt8196_adsp.dts

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/* Copyright 2024 The ChromiumOS Authors

 * SPDX-License-Identifier: Apache-2.0

 */

#include <mem.h>



/dts-v1/;

/ {



	#address-cells = <1>;

	#size-cells = <1>;



	sram0: memory@4e100000 {

		 device_type = "memory";

		 compatible = "mmio-sram";

		 reg = <0x4e100000 DT_SIZE_K(512)>;

	};



	dram0: memory@90000000 {

		device_type = "memory";

		compatible = "mmio-sram";

		reg = <0x90000000 DT_SIZE_M(6)>;

	};



	dram1: memory@90700000 {

		device_type = "memory";

		compatible = "mmio-sram";

		reg = <0x90700000 DT_SIZE_M(1)>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;



		core_intc: core_intc@0 {

			compatible = "cdns,xtensa-core-intc";

			reg = <0 4>;

			interrupt-controller;

			#interrupt-cells = <3>;

		};



		/* The 8196 interrupt controller is actually more complicated

		 * than the driver here supports.  There are 64 total

		 * interrupt inputs, each of which is a associated with one of

		 * 16 "groups", each of which is wired to a separate Xtensa

		 * architectural interrupt. (Whether the mapping of external

		 * interrupts to groups is mutable is an open question, the

		 * values here appear to be hardware defaults).  We represent

		 * each group (strictly each of the high and low 32 interrupts

		 * of each group) as a separate adsp_intc controller, pointing

		 * at the same status and enable registers, but with disjoint

		 * masks.  Note that this disallows configurations where a

		 * single controller needs to manage interrupts in both the

		 * high and low 32 bits of the set, but no current drivers

		 * rely on such a configuration.

		 */



		intc_g1: intc_g1@1a014010 {

			compatible = "mediatek,adsp_intc";

			interrupt-controller;

			#interrupt-cells = <3>;

			reg = <0x1a014010 4>;

			status-reg = <0x1a014008>;

			mask = <0x00007f3f>;

			interrupts = <1 0 0>;

			interrupt-parent = <&core_intc>;

		};



		intc_g2: intc_g2@1a014010 {

			compatible = "mediatek,adsp_intc";

			interrupt-controller;

			#interrupt-cells = <3>;

			reg = <0x1a014010 4>;

			status-reg = <0x1a014008>;

			mask = <0x000000c0>;

			interrupts = <2 0 0>;

			interrupt-parent = <&core_intc>;

		};



		ostimer64: ostimer64@1a00b080 {

			compatible = "mediatek,ostimer64";

			reg = <0x1a00b080 28>;

		};



		ostimer0: ostimer@1a00b000 {

			compatible = "mediatek,ostimer";

			reg = <0x1a00b000 16>;

			interrupt-parent = <&intc_g1>;

			interrupts = <8 0 0>;

		};



		mbox0: mbox@1a360100 {

			compatible = "mediatek,mbox";

			reg = <0x1a360100 16>;

			interrupt-parent = <&intc_g2>;

			interrupts = <6 0 0>;

		};



		mbox1: mbox@1a370100 {

			compatible = "mediatek,mbox";

			reg = <0x1a370100 16>;

			interrupt-parent = <&intc_g2>;

			interrupts = <7 0 0>;

		};

	}; /* soc */



	chosen { };

	aliases { };



};

boards/mediatek/twister.yaml

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@@ -14,3 +14,5 @@ variants: 
    name: MediaTek MT8188 Audio DSP

  mt8186/mt8186/adsp:

    name: MediaTek MT8186 Audio DSP

  mt8196/mt8196/adsp:

    name: MediaTek MT8196 Audio DSP

drivers/timer/mtk_adsp_timer.c

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@@ -56,8 +56,13 @@ struct mtk_ostimer64 { 
#define OSTIMER_CON_CLKSRC_BCLK 0x20 /*  CPU speed, 720 MHz */

#define OSTIMER_CON_CLKSRC_PCLK 0x30 /*  ~312 MHz experimentally */



#ifndef CONFIG_SOC_MT8196

#define OSTIMER_IRQ_ACK_ENABLE BIT(4) /*  read = status, write = enable */

#define OSTIMER_IRQ_ACK_CLEAR  BIT(5)

#else

#define OSTIMER_IRQ_ACK_ENABLE BIT(0)

#define OSTIMER_IRQ_ACK_CLEAR  BIT(5)

#endif



#define OST64_HZ 13000000U

#define OST_HZ 26000000U

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