Commit fe57a12c authored by Lucas Tamborrino's avatar Lucas Tamborrino Committed by Carles Cufi
Browse files

drivers: esp32: update to hal_espressif v5.1 



Modify necessary drivers to meet updated hal.

Signed-off-by: default avatarLucas Tamborrino <lucas.tamborrino@espressif.com>
Signed-off-by: default avatarSylvio Alves <sylvio.alves@espressif.com>
parent 37f9958f

drivers/adc/adc_esp32.c

+8 −23
Original line number Diff line number Diff line
@@ -10,42 +10,27 @@ 
#include <hal/adc_hal.h>

#include <hal/adc_types.h>

#include <esp_adc_cal.h>

#include <esp_heap_caps.h>

#include <esp_private/periph_ctrl.h>



#include <zephyr/kernel.h>

#include <zephyr/device.h>

#include <zephyr/drivers/adc.h>

#include "driver/periph_ctrl.h"



#include <zephyr/logging/log.h>

LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL);



#if CONFIG_SOC_SERIES_ESP32

#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_VREF

#define ADC_RESOLUTION_MIN	SOC_ADC_DIGI_MIN_BITWIDTH

#define ADC_RESOLUTION_MAX	SOC_ADC_DIGI_MAX_BITWIDTH



#if CONFIG_SOC_SERIES_ESP32

#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_VREF

/* Due to significant measurement discrepancy in higher voltage range, we

 * clip the value instead of yet another correction. The IDF implementation

 * for ESP32-S2 is doing it, so we copy that approach in Zephyr driver

 */

#define ADC_CLIP_MVOLT_11DB	2550



#elif CONFIG_SOC_SERIES_ESP32S2

#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_TP

#define ADC_RESOLUTION_MIN	SOC_ADC_DIGI_MAX_BITWIDTH

#define ADC_RESOLUTION_MAX	SOC_ADC_MAX_BITWIDTH



#elif CONFIG_SOC_SERIES_ESP32C3

#else

#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_TP

#define ADC_RESOLUTION_MIN	SOC_ADC_DIGI_MAX_BITWIDTH

#define ADC_RESOLUTION_MAX	SOC_ADC_DIGI_MAX_BITWIDTH



#elif CONFIG_SOC_SERIES_ESP32S3

#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_TP_FIT

#define ADC_RESOLUTION_MIN	SOC_ADC_DIGI_MIN_BITWIDTH

#define ADC_RESOLUTION_MAX	SOC_ADC_DIGI_MAX_BITWIDTH



#endif



/* Convert resolution in bits to esp32 enum values */
@@ -64,9 +49,9 @@ struct adc_esp32_conf { 
};



struct adc_esp32_data {

	adc_atten_t attenuation[ADC_CHANNEL_MAX];

	uint8_t resolution[ADC_CHANNEL_MAX];

	esp_adc_cal_characteristics_t chars[ADC_CHANNEL_MAX];

	adc_atten_t attenuation[SOC_ADC_MAX_CHANNEL_NUM];

	uint8_t resolution[SOC_ADC_MAX_CHANNEL_NUM];

	esp_adc_cal_characteristics_t chars[SOC_ADC_MAX_CHANNEL_NUM];

	uint16_t meas_ref_internal;

	uint16_t *buffer;

	uint16_t *buffer_repeat;
@@ -334,7 +319,7 @@ static const struct adc_driver_api api_esp32_driver_api = { 
#define ESP32_ADC_INIT(inst)							\

										\

	static const struct adc_esp32_conf adc_esp32_conf_##inst = {		\

		.unit = DT_PROP(DT_DRV_INST(inst), unit),			\

		.unit = DT_PROP(DT_DRV_INST(inst), unit) - 1,			\

		.channel_count = DT_PROP(DT_DRV_INST(inst), channel_count),	\

	};									\

										\

drivers/clock_control/clock_control_esp32.c

+36 −34
Original line number Diff line number Diff line
@@ -14,29 +14,29 @@ 
#undef CPU_RESET_REASON

#define CPU_RESET_REASON SW_CPU_RESET

#include <zephyr/dt-bindings/clock/esp32_clock.h>

#include "esp32/rom/rtc.h"

#include "soc/dport_reg.h"

#include <esp32/rom/rtc.h>

#include <soc/dport_reg.h>

#elif defined(CONFIG_SOC_SERIES_ESP32S2)

#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7

#include <zephyr/dt-bindings/clock/esp32s2_clock.h>

#include "esp32s2/rom/rtc.h"

#include "soc/dport_reg.h"

#include <esp32s2/rom/rtc.h>

#include <soc/dport_reg.h>

#elif defined(CONFIG_SOC_SERIES_ESP32S3)

#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7

#include <zephyr/dt-bindings/clock/esp32s3_clock.h>

#include "esp32s3/rom/rtc.h"

#include "soc/dport_reg.h"

#include "esp32s3/clk.h"

#include <esp32s3/rom/rtc.h>

#include <soc/dport_reg.h>

#elif CONFIG_SOC_SERIES_ESP32C3

#define DT_CPU_COMPAT espressif_riscv

#include <zephyr/dt-bindings/clock/esp32c3_clock.h>

#include "esp32c3/rom/rtc.h"

#include <esp32c3/rom/rtc.h>

#include <soc/soc_caps.h>

#include <soc/soc.h>

#include <soc/rtc.h>

#endif /* CONFIG_SOC_SERIES_ESP32xx */



#include "esp_rom_sys.h"

#include <esp_rom_sys.h>

#include <esp_rom_uart.h>

#include <soc/rtc.h>

#include <soc/i2s_reg.h>

#include <soc/apb_ctrl_reg.h>
@@ -44,8 +44,10 @@ 
#include <hal/clk_gate_ll.h>

#include <soc.h>

#include <zephyr/drivers/clock_control.h>

#include <driver/periph_ctrl.h>

#include <hal/cpu_hal.h>

#include <esp_private/periph_ctrl.h>

#include <esp_private/esp_clk.h>

#include <esp_cpu.h>

#include <esp_rom_caps.h>



struct esp32_clock_config {

	int clk_src_sel;
@@ -54,21 +56,6 @@ struct esp32_clock_config { 
	int xtal_div;

};



static uint8_t const xtal_freq[] = {

#if defined(CONFIG_SOC_SERIES_ESP32) || \

	defined(CONFIG_SOC_SERIES_ESP32S3)

	[ESP32_CLK_XTAL_24M] = 24,

	[ESP32_CLK_XTAL_26M] = 26,

	[ESP32_CLK_XTAL_40M] = 40,

	[ESP32_CLK_XTAL_AUTO] = 0

#elif defined(CONFIG_SOC_SERIES_ESP32S2)

	[ESP32_CLK_XTAL_40M] = 40,

#elif defined(CONFIG_SOC_SERIES_ESP32C3)

	[ESP32_CLK_XTAL_32M] = 32,

	[ESP32_CLK_XTAL_40M] = 40,

#endif

};



static int clock_control_esp32_on(const struct device *dev,

				  clock_control_subsys_t sys)

{
@@ -377,7 +364,7 @@ static void esp32_clock_perip_init(void) 


		wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |

			SYSTEM_WIFI_CLK_BT_EN_M |

			SYSTEM_WIFI_CLK_UNUSED_BIT5 |

			SYSTEM_WIFI_CLK_I2C_CLK_EN |

			SYSTEM_WIFI_CLK_UNUSED_BIT12 |

			SYSTEM_WIFI_CLK_SDIO_HOST_EN;

	}
@@ -424,8 +411,14 @@ static void esp32_clock_perip_init(void) 
	/* Enable RNG clock. */

	periph_module_enable(PERIPH_RNG_MODULE);



	esp_rom_uart_tx_wait_idle(0);

	esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200);

	/* Enable TimerGroup 0 clock to ensure its reference counter will never

	 * be decremented to 0 during normal operation and preventing it from

	 * being disabled.

	 * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog

	 * registers (Flashboot protection included) will be reenabled, and some

	 * seconds later, will trigger an unintended reset.

	 */

	periph_module_enable(PERIPH_TIMG0_MODULE);

}

#endif /* CONFIG_SOC_SERIES_ESP32S3 */
@@ -472,7 +465,7 @@ static void esp32_clock_perip_init(void) 


		wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |

				SYSTEM_WIFI_CLK_BT_EN_M |

				SYSTEM_WIFI_CLK_UNUSED_BIT5 |

				SYSTEM_WIFI_CLK_I2C_CLK_EN |

				SYSTEM_WIFI_CLK_UNUSED_BIT12;

	}
@@ -529,10 +522,10 @@ static int clock_control_esp32_init(const struct device *dev) 
	if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {

		rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();



		clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel];

		clk_cfg.xtal_freq = cfg->xtal_freq_sel;

		clk_cfg.cpu_freq_mhz = cfg->cpu_freq;

		clk_cfg.slow_freq = rtc_clk_slow_freq_get();

		clk_cfg.fast_freq = rtc_clk_fast_freq_get();

		clk_cfg.slow_clk_src = rtc_clk_slow_freq_get();

		clk_cfg.fast_clk_src = rtc_clk_fast_freq_get();

		rtc_clk_init(clk_cfg);

	}
@@ -563,10 +556,19 @@ static int clock_control_esp32_init(const struct device *dev) 
	rtc_clk_cpu_freq_set_config(&new_config);



	/* Re-calculate the ccount to make time calculation correct */

	cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz);

	esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);



	esp32_clock_perip_init();



	uint32_t clock_hz = esp_clk_apb_freq();

#if ESP_ROM_UART_CLK_IS_XTAL

	clock_hz = esp_clk_xtal_freq();

#endif

	esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM);



#if !defined(ESP_CONSOLE_UART_NONE)

	esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, clock_hz, ESP_CONSOLE_UART_BAUDRATE);

#endif

	return 0;

}

drivers/counter/counter_esp32_tmr.c

+29 −31
Original line number Diff line number Diff line
@@ -9,10 +9,11 @@ 
/* Include esp-idf headers first to avoid redefining BIT() macro */

#include <soc/rtc_cntl_reg.h>

#include <soc/timer_group_reg.h>

#include <driver/periph_ctrl.h>

#include <periph_ctrl.h>

#include <driver/timer_types_legacy.h>

#include <soc/periph_defs.h>

#include <hal/timer_types.h>

#include <hal/timer_hal.h>

#include <hal/timer_ll.h>

#include <string.h>

#include <zephyr/drivers/counter.h>

#include <zephyr/spinlock.h>
@@ -80,22 +81,18 @@ static int counter_esp32_init(const struct device *dev) 


	timer_hal_init(&data->hal_ctx, cfg->group, cfg->index);

	data->alarm_cfg.callback = NULL;

	timer_hal_intr_disable(&data->hal_ctx);

	timer_hal_clear_intr_status(&data->hal_ctx);

	timer_hal_set_auto_reload(&data->hal_ctx, cfg->config.auto_reload);

	timer_hal_set_divider(&data->hal_ctx, cfg->config.divider);

	timer_hal_set_counter_increase(&data->hal_ctx, cfg->config.counter_dir);

	timer_hal_set_alarm_enable(&data->hal_ctx, cfg->config.alarm_en);

	if (cfg->config.intr_type == TIMER_INTR_LEVEL) {

		timer_hal_set_level_int_enable(&data->hal_ctx, true);

	}

	timer_hal_set_counter_value(&data->hal_ctx, 0);

	timer_hal_set_counter_enable(&data->hal_ctx, cfg->config.counter_en);

	esp_intr_alloc(cfg->irq_source,

			0,

			(ISR_HANDLER)counter_esp32_isr,

			(void *)dev,

			NULL);

	timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),

			     false);

	timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));

	timer_ll_enable_auto_reload(data->hal_ctx.dev, data->hal_ctx.timer_id,

				    cfg->config.auto_reload);

	timer_ll_set_clock_prescale(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.divider);

	timer_ll_set_count_direction(data->hal_ctx.dev, data->hal_ctx.timer_id,

				     cfg->config.counter_dir);

	timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.alarm_en);

	timer_ll_set_reload_value(data->hal_ctx.dev, data->hal_ctx.timer_id, 0);

	timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.counter_en);

	esp_intr_alloc(cfg->irq_source, 0, (ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);

	k_spin_unlock(&lock, key);



	return 0;
@@ -106,7 +103,7 @@ static int counter_esp32_start(const struct device *dev) 
	struct counter_esp32_data *data = dev->data;

	k_spinlock_key_t key = k_spin_lock(&lock);



	timer_hal_set_counter_enable(&data->hal_ctx, TIMER_START);

	timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_START);

	k_spin_unlock(&lock, key);



	return 0;
@@ -117,7 +114,7 @@ static int counter_esp32_stop(const struct device *dev) 
	struct counter_esp32_data *data = dev->data;

	k_spinlock_key_t key = k_spin_lock(&lock);



	timer_hal_set_counter_enable(&data->hal_ctx, TIMER_PAUSE);

	timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_PAUSE);

	k_spin_unlock(&lock, key);



	return 0;
@@ -128,7 +125,7 @@ static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks) 
	struct counter_esp32_data *data = dev->data;

	k_spinlock_key_t key = k_spin_lock(&lock);



	timer_hal_get_counter_value(&data->hal_ctx, (uint64_t *)ticks);

	*ticks = timer_ll_get_counter_value(data->hal_ctx.dev, data->hal_ctx.timer_id);

	k_spin_unlock(&lock, key);



	return 0;
@@ -146,13 +143,15 @@ static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id, 
	k_spinlock_key_t key = k_spin_lock(&lock);



	if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {

		timer_hal_set_alarm_value(&data->hal_ctx, (now + alarm_cfg->ticks));

		timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,

					 (now + alarm_cfg->ticks));

	} else {

		timer_hal_set_alarm_value(&data->hal_ctx, alarm_cfg->ticks);

		timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,

					 alarm_cfg->ticks);

	}



	timer_hal_intr_enable(&data->hal_ctx);

	timer_hal_set_alarm_enable(&data->hal_ctx, TIMER_ALARM_EN);

	timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id), true);

	timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_EN);

	data->alarm_cfg.callback = alarm_cfg->callback;

	data->alarm_cfg.user_data = alarm_cfg->user_data;

	k_spin_unlock(&lock, key);
@@ -167,8 +166,9 @@ static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id) 


	k_spinlock_key_t key = k_spin_lock(&lock);



	timer_hal_intr_disable(&data->hal_ctx);

	timer_hal_set_alarm_enable(&data->hal_ctx, TIMER_ALARM_DIS);

	timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),

			     false);

	timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_DIS);

	k_spin_unlock(&lock, key);



	return 0;
@@ -190,9 +190,7 @@ static uint32_t counter_esp32_get_pending_int(const struct device *dev) 
{

	struct counter_esp32_data *data = dev->data;



	timer_hal_get_intr_status_reg(&data->hal_ctx);



	return 0;

	return timer_ll_get_intr_status(data->hal_ctx.dev);

}



static uint32_t counter_esp32_get_top_value(const struct device *dev)
@@ -226,7 +224,7 @@ static void counter_esp32_isr(void *arg) 
		data->alarm_cfg.callback(dev, 0, now, data->alarm_cfg.user_data);

	}



	timer_hal_clear_intr_status(&data->hal_ctx);

	timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));

}



#define ESP32_COUNTER_GET_CLK_DIV(idx)						 \

drivers/dac/dac_esp32.c

+3 −5
Original line number Diff line number Diff line
@@ -13,9 +13,7 @@ 
#include <hal/rtc_io_types.h>

#include <hal/rtc_io_hal.h>

#include <hal/rtc_io_ll.h>

#include <hal/dac_hal.h>

#include <hal/dac_types.h>

#include "driver/dac_common.h"

#include "driver/dac.h"



#include <zephyr/logging/log.h>

LOG_MODULE_REGISTER(esp32_dac, CONFIG_DAC_LOG_LEVEL);
@@ -41,7 +39,7 @@ static int dac_esp32_channel_setup(const struct device *dev, 
{

	ARG_UNUSED(dev);



	if (channel_cfg->channel_id > DAC_CHANNEL_MAX) {

	if (channel_cfg->channel_id > SOC_DAC_CHAN_NUM) {

		LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);

		return -EINVAL;

	}
@@ -66,7 +64,7 @@ static int dac_esp32_init(const struct device *dev) 
	}



	if (clock_control_on(cfg->clock_dev,

		(clock_control_subsys_t) cfg->clock_subsys) != 0) {

		(clock_control_subsys_t) &cfg->clock_subsys) != 0) {

		LOG_ERR("DAC clock setup failed (%d)", -EIO);

		return -EIO;

	}

drivers/dma/dma_esp32_gdma.c

+17 −14
Original line number Diff line number Diff line
@@ -11,11 +11,11 @@ LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL); 


#include <hal/gdma_hal.h>

#include <hal/gdma_ll.h>

#include <gdma_channel.h>

#include <soc/gdma_channel.h>

#include <hal/dma_types.h>



#include <soc.h>

#include <soc/soc_memory_types.h>

#include <esp_memory_utils.h>

#include <errno.h>

#include <zephyr/kernel.h>

#include <zephyr/drivers/dma.h>
@@ -34,6 +34,8 @@ LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL); 
#endif



#define DMA_MAX_CHANNEL SOC_GDMA_PAIRS_PER_GROUP

#define ESP_DMA_M2M_ON  0

#define ESP_DMA_M2M_OFF 1



struct dma_esp32_data {

	gdma_hal_context_t hal;
@@ -181,10 +183,12 @@ static int dma_esp32_config_rx(const struct device *dev, struct dma_esp32_channe 


	gdma_ll_rx_reset_channel(data->hal.dev, dma_channel->channel_id);



	if (dma_channel->periph_id != SOC_GDMA_TRIG_PERIPH_M2M0) {

		gdma_ll_rx_connect_to_periph(data->hal.dev, dma_channel->channel_id,

					     dma_channel->periph_id);

	}

	gdma_ll_rx_connect_to_periph(

		data->hal.dev, dma_channel->channel_id,

		dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON

								    : ESP_DMA_M2M_OFF,

		dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON

								    : dma_channel->periph_id);



	if (config_dma->dest_burst_length) {

		/*
@@ -236,10 +240,12 @@ static int dma_esp32_config_tx(const struct device *dev, struct dma_esp32_channe 


	gdma_ll_tx_reset_channel(data->hal.dev, dma_channel->channel_id);



	if (dma_channel->periph_id != SOC_GDMA_TRIG_PERIPH_M2M0) {

		gdma_ll_tx_connect_to_periph(data->hal.dev, dma_channel->channel_id,

					     dma_channel->periph_id);

	}

	gdma_ll_tx_connect_to_periph(

		data->hal.dev, dma_channel->channel_id,

		dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON

								    : ESP_DMA_M2M_OFF,

		dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON

								    : dma_channel->periph_id);



	/*

	 * TX channel can always enable burst mode, no matter data alignment
@@ -288,9 +294,6 @@ static int dma_esp32_config(const struct device *dev, uint32_t channel, 


	dma_channel->channel_id = channel / 2;



	gdma_ll_enable_m2m_mode(data->hal.dev, dma_channel->channel_id,

				config_dma->channel_direction == MEMORY_TO_MEMORY);



	switch (config_dma->channel_direction) {

	case MEMORY_TO_MEMORY:

		/*
@@ -538,7 +541,7 @@ static int dma_esp32_init(const struct device *dev) 
		dma_channel = &config->dma_channel[i];

		dma_channel->cb = NULL;

		dma_channel->dir = DMA_UNCONFIGURED;

		dma_channel->periph_id = GDMA_TRIG_PERIPH_INVALID;

		dma_channel->periph_id = ESP_GDMA_TRIG_PERIPH_INVALID;

		memset(&dma_channel->desc, 0, sizeof(dma_descriptor_t));

	}

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