Commit fafaa582 authored by Marcin Niestroj's avatar Marcin Niestroj Committed by Benjamin Cabé
Browse files

drivers: clock: stm32: support STM32_CLOCK_DIV() 



Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.

HSE is selected in devicetree using:

   <&rcc STM32_SRC_HSE ...>;

HSE/2 can now be selected with:

   <&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;

This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.

Signed-off-by: default avatarMarcin Niestroj <m.niestroj@emb.dev>
parent db43d2c4

drivers/clock_control/clock_stm32_ll_common.c

+4 −0
Original line number Diff line number Diff line
@@ -469,6 +469,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, 
		return -ENOTSUP;

	}



	if (pclken->div) {

		*rate /= (pclken->div + 1);

	}



	return 0;

}

drivers/clock_control/clock_stm32_ll_h5.c

+4 −0
Original line number Diff line number Diff line
@@ -342,6 +342,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev, 
		return -ENOTSUP;

	}



	if (pclken->div) {

		*rate /= (pclken->div + 1);

	}



	return 0;

}

drivers/clock_control/clock_stm32_ll_h7.c

+4 −0
Original line number Diff line number Diff line
@@ -646,6 +646,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, 
		return -ENOTSUP;

	}



	if (pclken->div) {

		*rate /= (pclken->div + 1);

	}



	return 0;

}

drivers/clock_control/clock_stm32_ll_mp1.c

+5 −0
Original line number Diff line number Diff line
@@ -390,6 +390,11 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, 
	default:

		return -ENOTSUP;

	}



	if (pclken->div) {

		*rate /= (pclken->div + 1);

	}



	return 0;

}

drivers/clock_control/clock_stm32_ll_u5.c

+4 −0
Original line number Diff line number Diff line
@@ -357,6 +357,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev, 
		return -ENOTSUP;

	}



	if (pclken->div) {

		*rate /= (pclken->div + 1);

	}



	return 0;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE