Commit fac04490 authored by Aurelien Jarno's avatar Aurelien Jarno Committed by Anas Nashif
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soc: st: stm32: stm32g0x: enable ART flash cache accelerator



Enable instruction cache and prefetching on STM32G0X SoC family.

Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent 858e8c51
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+5 −1
Original line number Diff line number Diff line
@@ -16,8 +16,8 @@
#include <string.h>

#include <cmsis_core.h>
#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
#include <stm32_ll_system.h>
#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
#include <stm32_ll_bus.h>
#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */

@@ -81,6 +81,10 @@ static void stm32g0_disable_dead_battery(void)
 */
static int stm32g0_init(void)
{
	/* Enable ART Accelerator I-cache and prefetch */
	LL_FLASH_EnableInstCache();
	LL_FLASH_EnablePrefetch();

	/* Update CMSIS SystemCoreClock variable (HCLK) */
	/* At reset, system core clock is set to 16 MHz from HSI */
	SystemCoreClock = 16000000;