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Commit f80347ec authored by Filip Kokosinski's avatar Filip Kokosinski Committed by Carles Cufí
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dts/riscv/lowrisc: add `lowrisc,ibex` compatible string 



The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.

Signed-off-by: default avatarFilip Kokosinski <fkokosinski@antmicro.com>
parent b5859ece
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