drivers/clock_control: stm32u5: Fix on flash latency procedure

Instead of computing hclk freq use for flash latency setting after
setting the PLLs, do it right at the beginning of the function.
Indeed, first step of PLL configuration is to switch back sysclock
to HSI source (in case it was initially PLL).
In that case, flash latency is theoretically set in consistency with PLL
driver hclk. So we should "measure" hclk freq at that step rather than
once sysclock is back on HSI.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>