enc28j60: allow simultaneous reception and transmission

SPI bus is a shared resource between tx and rx processes.
The access to it must be synchronized to allow a rx process to
happen even when a tx process is taking place.
ECON1 register must be saved by the rx process and recovered
at the end to ensure that the tx process will continue operating
in the same register bank.

Change-Id: Ie9358bf02bef8ddb5bdf76c8847e998a627e5395
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>