Skip to content
Commit f45acb7d authored by Michal Sieron's avatar Michal Sieron Committed by Marti Bolivar
Browse files

dts: riscv: litex-vexriscv: Update for 32-bit CSRs 



Use register addresses and sizes from 32-bit CSR version

Signed-off-by: default avatarMichal Sieron <msieron@internships.antmicro.com>
parent 95d867e8
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment

CRA Git | Maintained and supported by SUSTech CRA and CCSE