Commit f2581995 authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Kumar Gala
Browse files

drivers/clock_control: Add clock_control on STM32L5 series 



Add clock_control driver for STM32L5.
It's based on L4/WB driver since it is similar IP.

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent 25ac5968

drivers/clock_control/CMakeLists.txt

+3 −2
Original line number Diff line number Diff line
@@ -26,8 +26,9 @@ else() 
  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X clock_stm32g0.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_wb.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_l5_wb.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X clock_stm32l4_l5_wb.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_l5_wb.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X clock_stm32g4.c)

endif()

endif()

drivers/clock_control/Kconfig.stm32

+3 −3
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ config CLOCK_STM32_SYSCLK_SRC_HSI 


config CLOCK_STM32_SYSCLK_SRC_MSI

	bool "MSI"

	depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX

	depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX

	help

	  Use MSI as source of SYSCLK
@@ -89,7 +89,7 @@ choice 


config CLOCK_STM32_PLL_SRC_MSI

	bool "MSI"

	depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX

	depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX

	help

	  Use MSI as source of PLL
@@ -120,7 +120,7 @@ source "drivers/clock_control/Kconfig.stm32f1" 
source "drivers/clock_control/Kconfig.stm32f2_f4_f7"

source "drivers/clock_control/Kconfig.stm32h7"

source "drivers/clock_control/Kconfig.stm32l0_l1"

source "drivers/clock_control/Kconfig.stm32l4_wb"

source "drivers/clock_control/Kconfig.stm32l4_l5_wb"

source "drivers/clock_control/Kconfig.stm32g0"

source "drivers/clock_control/Kconfig.stm32g4"

drivers/clock_control/Kconfig.stm32l4_wb→drivers/clock_control/Kconfig.stm32l4_l5_wb

+3 −3
Original line number Diff line number Diff line 
# STM32L4 and STM32WB PLL configuration options

# STM32L4, STM32L5 and STM32WB PLL configuration options



# Copyright (c) 2019 Linaro

# SPDX-License-Identifier: Apache-2.0



if SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX

if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX



config CLOCK_STM32_PLL_M_DIVISOR

	int "PLL divisor"
@@ -59,4 +59,4 @@ config CLOCK_STM32_MSI_PLL_MODE 
	help

	  Enable hardware auto-calibration with LSE.



endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
 
endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX

drivers/clock_control/clock_stm32_ll_common.c

+10 −10
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ static inline int stm32_clock_control_on(struct device *dev, 
		LL_AHB1_GRP1_EnableClock(pclken->enr);

		break;

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \

	defined(CONFIG_SOC_SERIES_STM32L5X) || \

	defined(CONFIG_SOC_SERIES_STM32F4X) || \

	defined(CONFIG_SOC_SERIES_STM32F7X) || \

	defined(CONFIG_SOC_SERIES_STM32F2X) || \
@@ -96,21 +97,19 @@ static inline int stm32_clock_control_on(struct device *dev, 
	case STM32_CLOCK_BUS_AHB2:

		LL_AHB2_GRP1_EnableClock(pclken->enr);

		break;

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||

		CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32F2X ||

		CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */

#endif /* CONFIG_SOC_SERIES_STM32_* */

	case STM32_CLOCK_BUS_APB1:

		LL_APB1_GRP1_EnableClock(pclken->enr);

		break;

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \

	defined(CONFIG_SOC_SERIES_STM32L5X) || \

	defined(CONFIG_SOC_SERIES_STM32F0X) || \

	defined(CONFIG_SOC_SERIES_STM32WBX) || \

	defined(CONFIG_SOC_SERIES_STM32G4X)

	case STM32_CLOCK_BUS_APB1_2:

		LL_APB1_GRP2_EnableClock(pclken->enr);

		break;

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||

		CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */

#endif /* CONFIG_SOC_SERIES_STM32_* */

#if !defined(CONFIG_SOC_SERIES_STM32F0X)

	case STM32_CLOCK_BUS_APB2:

		LL_APB2_GRP1_EnableClock(pclken->enr);
@@ -141,6 +140,7 @@ static inline int stm32_clock_control_off(struct device *dev, 
		LL_AHB1_GRP1_DisableClock(pclken->enr);

		break;

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \

	defined(CONFIG_SOC_SERIES_STM32L5X) || \

	defined(CONFIG_SOC_SERIES_STM32F4X) || \

	defined(CONFIG_SOC_SERIES_STM32F7X) || \

	defined(CONFIG_SOC_SERIES_STM32F2X) || \
@@ -148,20 +148,19 @@ static inline int stm32_clock_control_off(struct device *dev, 
	case STM32_CLOCK_BUS_AHB2:

		LL_AHB2_GRP1_DisableClock(pclken->enr);

		break;

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||

		CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32G4X */

#endif /* CONFIG_SOC_SERIES_STM32_* */

	case STM32_CLOCK_BUS_APB1:

		LL_APB1_GRP1_DisableClock(pclken->enr);

		break;

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \

	defined(CONFIG_SOC_SERIES_STM32L5X) || \

	defined(CONFIG_SOC_SERIES_STM32F0X) || \

	defined(CONFIG_SOC_SERIES_STM32WBX) || \

	defined(CONFIG_SOC_SERIES_STM32G4X)

	case STM32_CLOCK_BUS_APB1_2:

		LL_APB1_GRP2_DisableClock(pclken->enr);

		break;

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||

		CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */

#endif /* CONFIG_SOC_SERIES_STM32_* */

#if !defined(CONFIG_SOC_SERIES_STM32F0X)

	case STM32_CLOCK_BUS_APB2:

		LL_APB2_GRP1_DisableClock(pclken->enr);
@@ -211,11 +210,12 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock, 
		break;

	case STM32_CLOCK_BUS_APB1:

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \

	defined(CONFIG_SOC_SERIES_STM32L5X) || \

	defined(CONFIG_SOC_SERIES_STM32F0X) || \

	defined(CONFIG_SOC_SERIES_STM32WBX) || \

	defined(CONFIG_SOC_SERIES_STM32G4X)

	case STM32_CLOCK_BUS_APB1_2:

#endif

#endif /* CONFIG_SOC_SERIES_STM32_* */

#if defined(CONFIG_SOC_SERIES_STM32G0X)

	case STM32_CLOCK_BUS_APB2:

		/*

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