Commit 25ac5968 authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Kumar Gala
Browse files

dts/arm/st: Add l5 device tree basics and stm32l552x socs



Add l5 secure and non secure device tree files

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent 3057d801
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/*
 * Copyright (c) 2020 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */


#include <arm/armv8-m.dtsi>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m33";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
				arm,num-mpu-regions = <8>;
			};
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	soc {
		flash-controller@40022000 {
			compatible = "st,stm32l5-flash-controller";
			label = "FLASH_CTRL";
			reg = <0x40022000 0x400>;
			interrupts = <4 0>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "soc-nv-flash";
				label = "FLASH_STM32";
			};
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};
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/*
 * Copyright (c) 2020 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/l5/stm32l5.dtsi>
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/*
 * Copyright (c) 2020 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <mem.h>
#include <st/l5/stm32l552.dtsi>

/ {
	sram0: memory@20000000 {
		reg = <0x20000000 DT_SIZE_K(192)>;
	};

	soc {
		flash-controller@40022000 {
			flash0: flash@8000000 {
				reg = <0x08000000 DT_SIZE_K(512)>;
			};
		};
	};
};
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description: STM32 L5 flash controller

compatible: "st,stm32l5-flash-controller"

include: flash-controller.yaml