Commit f22d30b8 authored by Yusuf Ahmed's avatar Yusuf Ahmed Committed by David Leach
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tests/driver/adc: Add ADC accuracy test



These tests, that expects boards to be properly setup, allow one to
measure ADC value and compare to expected values.

Two tests are added. For one, a reference voltage is expected on the ADC
- and this value can be informed to the test via devicetree. The other
uses DAC to generate a value that is then read from ADC. This assumes
DAC is accurate. Naturally, one could make this a DAC test if ADC is
assumed to be accurate.

As the board setup involve connecting physical pins, they are behind
twister fixtures.

Signed-off-by: default avatarYusuf Ahmed <muhammed.ahmed@intel.com>
Signed-off-by: default avatarEderson de Souza <ederson.desouza@intel.com>
parent 6514b3b8
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# SPDX-License-Identifier: Apache-2.0

cmake_minimum_required(VERSION 3.20.0)

find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(dac_accuracy)

target_sources(app PRIVATE src/main.c)
target_sources_ifdef(CONFIG_REFERENCE_VOLTAGE_TEST app PRIVATE src/ref_volt.c)
target_sources_ifdef(CONFIG_DAC_SOURCE_TEST app PRIVATE src/dac_source.c)
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# Copyright (c) 2023 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0

mainmenu "ADC accuracy test"

source "Kconfig.zephyr"

# Workaround to have commas on function arguments
ZEPHYR_USER := zephyr,user

config DAC_SOURCE_TEST
	bool
	default y if $(dt_node_has_prop,/$(ZEPHYR_USER),dac)

config REFERENCE_VOLTAGE_TEST
	bool
	default y if $(dt_node_has_prop,/$(ZEPHYR_USER),reference_mv)

config NUMBER_OF_PASSES
	int "Number of passes"
	default 5
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ADC accuracy test

This test checks that ADC readings match an expected value. It is
done using two approaches:

 - DAC source: a board DAC pin is set to a known value, which is then
 read on an ADC one. If they match, the test passes.

 - Reference voltage: an ADC channel is read and compared to an expected
 value.

For the DAC source, it is expected that DAC and ADC are connected. This
can be indicated for twister runs by setting the fixture "dac_adc_loop".
The test then sets DAC to half its resolution and reads the ADC to see
if they match. Note that DAC and ADC are expected to generate/read
voltage on the same range.

In the reference voltage case, the ADC is expected to be connected to a
known voltage reference, whose value is informed, in millivolts, at
property "reference_mv" from "zephyr,user" node. The test reads the ADC
to see if they match.
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CONFIG_DAC=y
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/*
 * Copyright (c) 2023 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Please connect J4.3 and J4.11 together to run this test.
 * J4.3 will be the ADC input and J4.11 the DAC output
 */

/ {
	zephyr,user {
		io-channels = <&adc0 20>;
		dac = <&dac0>;
		dac-channel-id = <0>;
		dac-resolution = <12>;
	};
};

&adc0{
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	channel@14 {
		reg = <20>;
		zephyr,gain = "ADC_GAIN_1";
		zephyr,reference = "ADC_REF_INTERNAL";
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
		zephyr,resolution = <12>;
	};
};
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