Commit ebc5e51e authored by Yannis Damigos's avatar Yannis Damigos Committed by Kumar Gala
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dts/arm/st: Fix I2C3 clock property on L0 series 



Set the correct bit to enable I2C3 clock on L0
series.

Signed-off-by: default avatarYannis Damigos <giannis.damigos@gmail.com>
parent ce983e77

dts/arm/st/stm32l072.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40007800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;

			interrupts = <21 0>;

			interrupt-names = "combined";

			status = "disabled";

dts/arm/st/stm32l073.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40007800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;

			interrupts = <21 0>;

			interrupt-names = "combined";

			status = "disabled";

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