drivers: mspi: mspi_dw: improve reliability of CS signal

The designware controller has an *interesting* implementation of the CS
signal- CS will be de-asserted whenever the TX FIFO is empty, so slower
cores may see CS de-assert prematurely if they cannot keep pace with
their SPI peripheral. To help reduce odds of de-assertion, implement the
following changes:

- don't write SER bit until directly before we enable interrupts, so
  that transfers don't start early
- prefix the TX FIFO before writing SER, so the FIFO can drain a bit
  before have to service an interrupt

Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>