driver: timer: npcx: bypass timer counter reading issue

Originally, when the timer's source clock is 32.768 kHz, the timer driver
uses two consecutive reads to ensure the timer reading is correct.
However, it is not robust enough due to an asynchronous timing issue in
the chip. The workaround is to add at least two NOPs between the
LDR and CMP instructions. This commit implements the workaround in the
assembly code to ensure it is not affected by the compiler toolchain
or optimization flags.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
(cherry picked from commit 2bda7b87)