dts: xtensa: intel: Add hsbcap register node for ADSP ACE platforms

This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.

In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>