soc/intel_adsp: Fix MP startup for cAVS 2.5

This hardware works a little differently.  The cores will start up
immediately on receipt of an IDC interrupt (they don't need the host
to be involved), but they don't have a ROM.  They start executing at
the start of the LP-SRAM block always.  Copy over a tiny trampoline
for them that jumps to the existing multiprocessor startup path.

Also set the PS WOE bit to enable register windows in the startup
path.  This isn't the hardware default, and where the ROM would do
that for us before here we need to make sure it's on.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>