Commit d6990ff8 authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Carles Cufi
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dts: stm32l4: Add a comment on RNG clock configuration 



Explicit default RNG domain clock configuration constraints.

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent f48dfbf0

dts/arm/st/l4/stm32l4.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -448,6 +448,9 @@ 
			reg = <0x50060800 0x400>;

			interrupts = <80 0>;

			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,

				/* Following domain clock setting requires MSI

				 * clock to be enabled with msi-range = <11>;

				 */

				 <&rcc STM32_SRC_MSI CLK48_SEL(3)>;

			status = "disabled";

		};

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