Commit d280d892 authored by Harris Tomy's avatar Harris Tomy Committed by Dan Kalowsky
Browse files

dts/kconfig: stm32u5: add f9 and clean up dts node locations 



Adds skeleton dtsi for u5f9 for u5g9 to inherit from

Moves the peripheral nodes into dtsi's that actually has the peripheral
and includes them for SoC's higher in the series where applicable.

signed-off-by: default avatarHarris Tomy <harristomy@gmail.com>
parent 97876b5d

boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
/dts-v1/;

#include <st/u5/stm32u5g9Xj.dtsi>

#include <st/u5/stm32u5g9zjtxq-pinctrl.dtsi>

#include <zephyr/dt-bindings/display/panel.h>

#include <zephyr/dt-bindings/input/input-event-codes.h>



/ {

dts/arm/st/u5/stm32u5.dtsi

+1 −80
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * Copyright (c) 2021 Linaro Limited

 * Copyright (c) 2023 PSICONTROL nv

 * Copyright (c) 2024 STMicroelectronics

 * Copyright (c) 2025 Harris Tomy

 *

 * SPDX-License-Identifier: Apache-2.0

 */
@@ -17,7 +18,6 @@ 
#include <zephyr/dt-bindings/flash_controller/ospi.h>

#include <zephyr/dt-bindings/reset/stm32u5_reset.h>

#include <zephyr/dt-bindings/dma/stm32_dma.h>

#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>

#include <zephyr/dt-bindings/adc/stm32u5_adc.h>

#include <zephyr/dt-bindings/power/stm32_pwr.h>

#include <freq.h>
@@ -253,14 +253,6 @@ 
				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;

			};



			gpiof: gpio@42021400 {

				compatible = "st,stm32-gpio";

				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x42021400 0x400>;

				clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;

			};



			gpiog: gpio@42021800 {

				compatible = "st,stm32-gpio";

				gpio-controller;
@@ -276,14 +268,6 @@ 
				reg = <0x42021c00 0x400>;

				clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;

			};



			gpioi: gpio@42022000 {

				compatible = "st,stm32-gpio";

				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x42022000 0x400>;

				clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;

			};

		};



		iwdg: watchdog@40003000 {
@@ -318,15 +302,6 @@ 
			status = "disabled";

		};



		usart2: serial@40004400 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40004400 0x400>;

			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;

			resets = <&rctl STM32_RESET(APB1L, 17U)>;

			interrupts = <62 0>;

			status = "disabled";

		};



		usart3: serial@40004800 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40004800 0x400>;
@@ -731,28 +706,6 @@ 
			status = "disabled";

		};



		octospi2: spi@420d2400 {

			compatible = "st,stm32-ospi";

			reg = <0x420d2400 0x400>;

			interrupts = <120 0>;

			clock-names = "ospix", "ospi-ker", "ospi-mgr";

			clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>,

				<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,

				<&rcc STM32_CLOCK(AHB2, 21U)>;

			#address-cells = <1>;

			#size-cells = <1>;

			status = "disabled";

		};



		aes: aes@420c0000 {

			compatible = "st,stm32-aes";

			reg = <0x420c0000 0x400>;

			clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;

			resets = <&rctl STM32_RESET(AHB2L, 16U)>;

			interrupts = <93 0>;

			status = "disabled";

		};



		rng: rng@420c0800 {

			compatible = "st,stm32-rng";

			reg = <0x420c0800 0x400>;
@@ -782,16 +735,6 @@ 
			status = "disabled";

		};



		sdmmc2: sdmmc@420c8c00 {

			compatible = "st,stm32-sdmmc";

			reg = <0x420c8c00 0x400>;

			clocks = <&rcc STM32_CLOCK(AHB2, 28U)>,

				 <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;

			resets = <&rctl STM32_RESET(AHB2L, 28U)>;

			interrupts = <79 0>;

			status = "disabled";

		};



		dac1: dac@46021800 {

			compatible = "st,stm32-dac";

			reg = <0x46021800 0x400>;
@@ -848,14 +791,6 @@ 
			status = "disabled";

		};



		ucpd1: ucpd@4000dc00 {

			compatible = "st,stm32-ucpd";

			reg = <0x4000dc00 0x400>;

			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;

			interrupts = <106 0>;

			status = "disabled";

		};



		gpdma1: dma@40020000 {

			compatible = "st,stm32u5-dma";

			#dma-cells = <3>;
@@ -869,20 +804,6 @@ 
			status = "disabled";

		};



		fmc: memory-controller@420d0400 {

			compatible = "st,stm32-fmc";

			reg = <0x420d0400 0x400>;

			clocks = <&rcc STM32_CLOCK(AHB2_2, 0U)>;

			status = "disabled";



			sram {

				compatible = "st,stm32-fmc-nor-psram";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};

		};



		pwr: power@46020800 {

			compatible = "st,stm32-pwr";

			reg = <0x46020800 0x400>; /* PWR register bank */

dts/arm/st/u5/stm32u535.dtsi

+10 −25
Original line number Diff line number Diff line
@@ -4,35 +4,20 @@ 
 * SPDX-License-Identifier: Apache-2.0

 */



#include <st/u5/stm32u5.dtsi>

#include <st/u5/stm32u5_usb_fs.dtsi>



/ {

	soc {

		/* USB-C PD is not available on this part. */

		/delete-node/ ucpd@4000dc00;



		/* Advanced Encryption Standard HW accelerator is not available on this part. */

		/delete-node/ aes@420c0000;



		compatible = "st,stm32u535", "st,stm32u5", "simple-bus";



		usb: usb@40016000 {

			compatible = "st,stm32-usb";

			reg = <0x40016000 0x400>;

			interrupts = <73 0>;

			interrupt-names = "usb";

			num-bidir-endpoints = <8>;

			ram-size = <2048>;

			maximum-speed = "full-speed";

			clocks = <&rcc STM32_CLOCK(APB2, 24)>,

				<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;

			phys = <&usb_fs_phy>;

			status = "disabled";

	sram0: memory@20000000 {

		/* SRAM1 + SRAM2 */

		reg = <0x20000000 DT_SIZE_K(256)>;

	};



	sram1: memory@28000000 {

		/* SRAM4, low-power background autonomous mode */

		reg = <0x28000000 DT_SIZE_K(16)>;

	};



	usb_fs_phy: usb_fs_phy {

		compatible = "usb-nop-xceiv";

		#phy-cells = <0>;

	soc {

		compatible = "st,stm32u535", "st,stm32u5", "simple-bus";

	};

};

dts/arm/st/u5/stm32u535Xb.dtsi

+0 −10
Original line number Diff line number Diff line
@@ -8,16 +8,6 @@ 
#include <st/u5/stm32u535.dtsi>



/ {

	sram0: memory@20000000 {

		/* SRAM1 + SRAM2 */

		reg = <0x20000000 DT_SIZE_K(256)>;

	};



	sram1: memory@28000000 {

		/* SRAM4, low-power background autonomous mode */

		reg = <0x28000000 DT_SIZE_K(16)>;

	};



	soc {

		flash-controller@40022000 {

			flash0: flash@8000000 {

dts/arm/st/u5/stm32u535Xc.dtsi

+0 −10
Original line number Diff line number Diff line
@@ -8,16 +8,6 @@ 
#include <st/u5/stm32u535.dtsi>



/ {

	sram0: memory@20000000 {

		/* SRAM1 + SRAM2 */

		reg = <0x20000000 DT_SIZE_K(256)>;

	};



	sram1: memory@28000000 {

		/* SRAM4, low-power background autonomous mode */

		reg = <0x28000000 DT_SIZE_K(16)>;

	};



	soc {

		flash-controller@40022000 {

			flash0: flash@8000000 {

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