dts: stm32u5: add memory package variants (97876b5d) · Commits · Wenxi XU / zephyr

dts/arm/st/u5/stm32u535Xb.dtsi

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		/*
		* Copyright (c) 2025 Harris Tomy
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <mem.h>
		#include <st/u5/stm32u535.dtsi>

		/ {
		sram0: memory@20000000 {
		/* SRAM1 + SRAM2 */
		reg = <0x20000000 DT_SIZE_K(256)>;
		};

		sram1: memory@28000000 {
		/* SRAM4, low-power background autonomous mode */
		reg = <0x28000000 DT_SIZE_K(16)>;
		};

		soc {
		flash-controller@40022000 {
		flash0: flash@8000000 {
		reg = <0x08000000 DT_SIZE_K(128)>;
		};
		};
		};
		};

0 → 100644

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Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2025 Harris Tomy
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <mem.h>
		#include <st/u5/stm32u535.dtsi>

		/ {
		sram0: memory@20000000 {
		/* SRAM1 + SRAM2 */
		reg = <0x20000000 DT_SIZE_K(256)>;
		};

		sram1: memory@28000000 {
		/* SRAM4, low-power background autonomous mode */
		reg = <0x28000000 DT_SIZE_K(16)>;
		};

		soc {
		flash-controller@40022000 {
		flash0: flash@8000000 {
		reg = <0x08000000 DT_SIZE_K(256)>;
		};
		};
		};
		};

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		/*
		* Copyright (c) 2025 Harris Tomy
		*
		* SPDX-License-Identifier: Apache-2.0
		*/
		#include <mem.h>
		#include <st/u5/stm32u575.dtsi>

		/ {
		sram0: memory@20000000 {
		/* SRAM1 + SRAM2 + SRAM3 */
		reg = <0x20000000 DT_SIZE_K(768)>;
		};

		sram1: memory@28000000 {
		/* SRAM4, low-power background autonomous mode */
		reg = <0x28000000 DT_SIZE_K(16)>;
		};

		soc {
		flash-controller@40022000 {
		flash0: flash@8000000 {
		reg = <0x08000000 DT_SIZE_M(1)>;
		};
		};
		};
		};