Commit d1614851 authored by Huifeng Zhang's avatar Huifeng Zhang Committed by Fabio Baltieri
Browse files

boards: fvp_baser_aemv8r: fix wrong reg size 



Some reg size in fvp-aemv8r.dtsi isn't correct. This commit is used to
fix it.

- gic, the correct reg size is 0x10000 and 0x200000.
- uart0-3, the correct reg size is 0x10000.

Signed-off-by: default avatarHuifeng Zhang <Huifeng.Zhang@arm.com>
parent 3ef14cae

dts/arm64/fvp/fvp-aemv8r.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -61,8 +61,8 @@ 


		gic: interrupt-controller@af000000 {

			compatible = "arm,gic";

			reg = <0xaf000000 0x1000>,

			      <0xaf100000 0x100>;

			reg = <0xaf000000 0x10000>,

			      <0xaf100000 0x200000>;

			interrupt-controller;

			#interrupt-cells = <4>;

			status = "okay";
@@ -70,7 +70,7 @@ 


		uart0: uart@9c090000 {

			compatible = "arm,pl011";

			reg = <0x9c090000 0x1000>;

			reg = <0x9c090000 0x10000>;

			status = "disabled";

			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_5";
@@ -79,7 +79,7 @@ 


		uart1: uart@9c0a0000 {

			compatible = "arm,pl011";

			reg = <0x9c0a0000 0x1000>;

			reg = <0x9c0a0000 0x10000>;

			status = "disabled";

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_6";
@@ -88,7 +88,7 @@ 


		uart2: uart@9c0b0000 {

			compatible = "arm,pl011";

			reg = <0x9c0b0000 0x1000>;

			reg = <0x9c0b0000 0x10000>;

			status = "disabled";

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_7";
@@ -97,7 +97,7 @@ 


		uart3: uart@9c0c0000 {

			compatible = "arm,pl011";

			reg = <0x9c0c0000 0x1000>;

			reg = <0x9c0c0000 0x10000>;

			status = "disabled";

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_8";

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