Commit 3ef14cae authored Jul 05, 2022 by Huifeng Zhang Committed by Fabio Baltieri Sep 09, 2022

arch: arm64: init VMPIDR_EL2 in z_arm64_el2_init

VMPIDR_EL2 is assigned the value returned by EL2 reads of MPIDR_EL1

MPIDR_EL1 is the register holding the Multiprocessor ID which is to
identify different cores. Because of the virtualization requirements
for AArch64, MPIDR_EL1 should be virtualized (the different virtualized
cores can run on the same physical core). Thus the value of MPIDR_EL1
should be switched when the VM is switched. Setting the VMPIDR_EL2 is
the way to change the value returned by EL1 reads of MPIDR_EL1. Even
without virtualization, we still need to set VMPIDR_EL2 during booting
at EL2 or EL3. Otherwise, all cores' IDs are zero at the EL1 stage
which will break the SMP system.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>

parent dab22aac

arch/arm64/core/Kconfig

+8 −0

Original line number	Diff line number	Diff line
		@@ -193,6 +193,14 @@ config EXCEPTION_DEBUG
		config XIP
		select AARCH64_IMAGE_HEADER

		config ARM64_SET_VMPIDR_EL2
		bool "Set VMPIDR_EL2 at EL2 stage"
		help
		VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
		This is the value returned by EL1 reads of MPIDR_EL1.
		This register may already be set by bootloader at the EL2 stage, if
		not, Zephyr should set it.

		if ARM_MMU

		config MMU_PAGE_SIZE

arch/arm64/core/reset.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -136,6 +136,12 @@ void z_arm64_el2_init(void)
		#else
		zero_cnthp_ctl_el2();
		#endif

		#ifdef CONFIG_ARM64_SET_VMPIDR_EL2
		reg = read_mpidr_el1();
		write_vmpidr_el2(reg);
		#endif

		/*
		* Enable this if/when we use the hypervisor timer.
		* write_cnthp_cval_el2(~(uint64_t)0);

Admin message