boards: nordic: ipc: added dcache alignement

The nRF54 and nRF92 chips has data cache, which means
the ICMsg and ICBMsg must be configured to follow required
cache alignment of the shared memory.
The `dcache-alignement` needs to be defined for that.

Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>