ARC: correctly generate the SW IRQ table

Too many entries were being created in this table. It needs to
create indexes starting from 16 to CONFIG_NUM_IRQS - 1, since IRQS 0-15
are reserved for CPU exceptions and are not handled through this
mechanism.

generic_arc was still using the old C-based table which is
incompatible with the static IRQ implementation. An attempt was made
to move the SW IRQ table to arch/arc/core, but linker issues were
encountered and this will be done in another patch.

With CONFIG_NUM_IRQS set to 68 on Quark SE, inspection of binary
with objdump -x reveals that we are generating table entries:

00000000 g     O .isr_irq16	00000000 _sw_isr_table
00000000  w    O .gnu.linkonce.isr_irq16	00000000 _isr_irq16
00000000  w    O .gnu.linkonce.isr_irq17	00000000 _isr_irq17
00000000  w    O .gnu.linkonce.isr_irq18	00000000 _isr_irq18
...
00000000  w    O .gnu.linkonce.isr_irq67	00000000 _isr_irq67

Which is exactly what we need.

Change-Id: I8ca1682128ae67e2a24642791b7ce31ebca759bf
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>