drivers/clock_control: stm32 common: enable PLL_P/Q and set PLL_P div

This commit configures the PLL_P divider for SOCs compatible to the
stm32_ll_common driver in case a value was defined via a dts property.

Additionally, in case the divider value is defined in the device
tree, the respective pll output is enabled during initialization
in set_up_plls().

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>