drivers: clock_control: stm32f3: Enable PWR clock to access BDCR and PWR_CR

BDCR and PWR_CR could be required for LSE or RTC for instance.
Enable it here as for now, no sophisticated PM handling is available
on F0 and F3 series.

Fixes #56449
Fixup for #56505

Signed-off-by: Kay P <kayo@illumium.org>