[drivers]: gpios: SN74HC595: Extend to allow for chained shift registers

The current driver has a few limitations:
1. The `ngpios` DT property is fixed at eight.
   Since the SN74HC595 and kin are designed to be
   easily daisychain-able, the upper bound on `ngpios`
   should be limited only by the maximum number of pins
   that Zephyr supports per GPIO port, which is 32.
2. In the case of having no control over the shift register's
   reset input, the device tree node should accept a default
   value to shift into the register(s) during init.
3. There seems to be an assumption that the serial clock
   and load clock are tied together. While this is often the
   case, the device tree node should be more flexible in
   allowing the specification of a separate load clock GPIO pin.
4. The device tree node should also be able to accept a GPIO pin
   to drive the enable input pin of the shift register(s).

This commit addresses all of these issues.

Signed-off-by: Pete Dietl <petedietl@gmail.com>