soc: ti: k3: am6x: m4: Lock resource table location in DRAM

Currently the resource table is added to the memory-region labeled DDR.
This region can also be extra space for code/data, although this is
not yet implemented. This will mean that the linker is free to put
the resource table *after* the code/data sections in DDR. The resource
table must be at the start of the assigned DRAM area for the remote
core to support early-boot/late-attach usecases.

To solve this, we carveout the first 4KB of our DRAM area specifically
for the resource table. This matches how this issue was solved for the
K3 R5F cores.

To make this clear we label this memory-region "RSC_TABLE". This is
done at the linker file level, which is common for all K3 M4 boards
and so we update all 3 such boards in this one patch instead of
patch-per-board.

Signed-off-by: Andrew Davis <afd@ti.com>