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Commit c01a8c88 authored by Marcin Szkudlinski's avatar Marcin Szkudlinski Committed by Anas Nashif
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mtl: soc: store power gating state in D3 state 



Power gating register must be stored when CPU is in
power off state

Signed-off-by: default avatarMarcin Szkudlinski <marcin.szkudlinski@intel.com>
parent 1631d2dc
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