Commit bc915ef5 authored by Steven Shen's avatar Steven Shen Committed by Anas Nashif
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arch: arm64: Fix ICC_SGI1R mask for arm64 



According to "Arm A-profile Architecture Registers",
Interrupt Controller Software Generaated Interrupt
Group 1 Register (ICC_SGI1R), AFF is 8 bits width
and the mask should be 0xFF but not 0xF.

Cortex_a_r is okay and no need to be fixed.

Signed-off-by: default avatarSteven Shen <steven.shen@jaguarmicro.com>
Tested-by: default avatarRex Nie <rex.nie@jaguarmicro.com>
parent bf6ba176

include/zephyr/arch/arm64/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -171,7 +171,7 @@ 
#define SGIR_AFF1_SHIFT		(16)

#define SGIR_AFF2_SHIFT		(32)

#define SGIR_AFF3_SHIFT		(48)

#define SGIR_AFF_MASK		(0xf)

#define SGIR_AFF_MASK		(0xff)

#define SGIR_INTID_SHIFT	(24)

#define SGIR_INTID_MASK		(0xf)

#define SGIR_IRM_SHIFT		(40)

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