drivers: can: stm32h7: fdcan: add support for domain clock and divider

Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.

Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>