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Commit bc2a0b65 authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Carles Cufí
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tests/drivers/clock_control: stm32u5: Fix pll_msis_80 test config 



PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent 424f937c
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