spi: sam0: fix CS and back-to-back transfers.

Fixes #6577.

Wait for all ongoing transmits to complete before de-asserting CS.

When doing a tx then rx, wait for the previous tx to complete before
flushing the rx buffer.

Tested on the Arduino Zero against a Olimex MOD-NRF24L module.

Signed-off-by: Michael Hope <mlhx@google.com>