drivers: entropy: stm32: Configure clock source using clock_control driver

RNG domain source clock is now configured via call to clock_control
driver.
Besides, add static checks to verify domain clock configuration
is correct:
- If HSI48 is used because it is default domain clock config,
it should be enabled
- If no HSI48 is available, a specific domain clock should be set
- In L0 case, PLL could be used as domain clock only at a specific freq.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>