soc: intel_adsp: Unbreak older cAVS devices

On pre-2.5 cAVS, the initial IDC interrupt to start the other core is
handled by software in the firmware ROM.  That means that it has to be
unmasked for the mechanism to work (with 2.5, the interrupt is handled
by hardware regardless of what the masking state in the interrupt
controller is).

Similarly, the Xtensa Region Protection Option entries have already
been set by ROM code when we arrive in enable_l1_cache(), so we can
skip that part on older machines.  Also removed because trying to
rewrite those entries was causing inexplicable hangs on cAVS 1.5,
plausibly because the region had active cache lines.

(This patch is separate for easier review in a long evolving PR.
Technically it represents a bisection problem as the "New IDC Driver"
patch before this was a regression.  Seems like a safe enough thing to
handle if you land on this.)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>