drivers: clock_control: add Aspeed AST10x0 clock control

AST10x0 series SOCs provide the clock controller through the syscon
hardware block.  The current driver supports the clock gating capability
for the hardware IPs embedded in the SOC.  Each clock source has a
clock ID that can simply map to a bit in syscon registers CLK_STOP_CTRL0
(group 0) or CLK_STOP_CTRL1 (group 1).  There are some clock sources
that don't have associated clock gating control, which are always on,
are grouped to into group 2.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>