arch/x86: Fixing dcache enable/disable code

It did not build in x86_64 due to the fact that cr0 is a 64bits
register in such architecture, instead of being a 32bits one originaly
so the place holder has to follow that size. Such place holder must be
initialized to 0 to make sure no upper 32 bits ends up set which would
conclude in a general protection error.

Operand size specifier (l, q ...) is useless as well in this context.

Clearing up the masks by using proper macros.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>