drivers: hwinfo: mcux_src_rev2: Update to support MIMXRT118X (affb8368) · Commits · Wenxi XU / zephyr

drivers/hwinfo/hwinfo_mcux_src_rev2.c

+49 −3

Original line number	Diff line number	Diff line
		@@ -11,6 +11,10 @@
		#include <string.h>
		#include <zephyr/sys/byteorder.h>

		#if defined(CONFIG_SOC_SERIES_IMXRT11XX)

		#define MCUX_SRC_TYPE SRC_Type

		#ifdef CONFIG_CPU_CORTEX_M7
		#define MCUX_RESET_PIN_FLAG SRC_SRSR_IPP_USER_RESET_B_M7_MASK
		#define MCUX_RESET_SOFTWARE_FLAG SRC_SRSR_M7_LOCKUP_M7_MASK
		@@ -36,19 +40,51 @@
		#error "MCUX SRC driver not supported for this CPU!"
		#endif

		#elif defined(CONFIG_SOC_SERIES_IMXRT118X)

		#define MCUX_SRC_TYPE SRC_GENERAL_Type

		#define MCUX_RESET_PIN_FLAG SRC_GENERAL_SRSR_IPP_POR_B_MASK
		#define MCUX_RESET_POR_FLAG SRC_GENERAL_SRSR_POR_RST_MASK
		#define MCUX_RESET_WATCHDOG_FLAG \
		(SRC_GENERAL_SRSR_WDOG1_RST_B_MASK \| SRC_GENERAL_SRSR_WDOG2_RST_B_MASK \| \
		SRC_GENERAL_SRSR_WDOG3_RST_B_MASK \| SRC_GENERAL_SRSR_WDOG4_RST_B_MASK \| \
		SRC_GENERAL_SRSR_WDOG5_RST_B_MASK)
		#define MCUX_RESET_DEBUG_FLAG SRC_GENERAL_SRSR_JTAG_SW_RST_MASK
		#define MCUX_RESET_SECURITY_FLAG SRC_GENERAL_SRSR_EDGELOCK_RESET_B_MASK
		#define MCUX_RESET_TEMPERATURE_FLAG SRC_GENERAL_SRSR_TEMPSENSE_RST_B_MASK

		#if defined(CONFIG_CPU_CORTEX_M7)
		#define MCUX_RESET_USER_FLAG SRC_GENERAL_SRSR_CM7_REQUEST_MASK
		#define MCUX_RESET_CPU_LOCKUP_FLAG SRC_GENERAL_SRSR_CM7_LOCKUP_MASK
		#elif defined(CONFIG_CPU_CORTEX_M33)
		#define MCUX_RESET_USER_FLAG SRC_GENERAL_SRSR_CM33_REQUEST_MASK
		#define MCUX_RESET_CPU_LOCKUP_FLAG SRC_GENERAL_SRSR_CM33_LOCKUP_MASK
		#else
		/* The SOCs currently supported have an M7 or M33 core */
		#error "MCUX SRC driver not supported for this CPU!"
		#endif

		#else
		/* Only support RT116x/RT117x/RT118x. */
		#error "MCUX SRC driver not supported for this SOC!"
		#endif

		BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found");

		int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
		{
		uint32_t flags = 0;
		uint32_t reason = ((SRC_Type *)DT_INST_REG_ADDR(0))->SRSR;
		uint32_t reason = ((MCUX_SRC_TYPE *)DT_INST_REG_ADDR(0))->SRSR;

		if (reason & (MCUX_RESET_PIN_FLAG)) {
		flags \|= RESET_PIN;
		}
		#if defined(MCUX_RESET_SOFTWARE_FLAG)
		if (reason & (MCUX_RESET_SOFTWARE_FLAG)) {
		flags \|= RESET_SOFTWARE;
		}
		#endif /* MCUX_RESET_SOFTWARE_FLAG */
		if (reason & (MCUX_RESET_POR_FLAG)) {
		flags \|= RESET_POR;
		}
		@@ -67,6 +103,11 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
		if (reason & (MCUX_RESET_USER_FLAG)) {
		flags \|= RESET_USER;
		}
		#if defined(MCUX_RESET_CPU_LOCKUP_FLAG)
		if (reason & (MCUX_RESET_CPU_LOCKUP_FLAG)) {
		flags \|= RESET_CPU_LOCKUP;
		}
		#endif /* MCUX_RESET_CPU_LOCKUP_FLAG */

		*cause = flags;

		@@ -75,9 +116,9 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause)

		int z_impl_hwinfo_clear_reset_cause(void)
		{
		uint32_t reason = ((SRC_Type *)DT_INST_REG_ADDR(0))->SRSR;
		uint32_t reason = ((MCUX_SRC_TYPE *)DT_INST_REG_ADDR(0))->SRSR;

		((SRC_Type *)DT_INST_REG_ADDR(0))->SRSR = reason;
		((MCUX_SRC_TYPE *)DT_INST_REG_ADDR(0))->SRSR = reason;

		return 0;
		}
		@@ -88,10 +129,15 @@ int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
		\| RESET_DEBUG
		\| RESET_TEMPERATURE
		\| RESET_PIN
		#if defined(MCUX_RESET_SOFTWARE_FLAG)
		\| RESET_SOFTWARE
		#endif
		\| RESET_POR
		\| RESET_SECURITY
		\| RESET_USER
		#if defined(MCUX_RESET_CPU_LOCKUP_FLAG)
		\| RESET_CPU_LOCKUP
		#endif
		);

		return 0;

dts/arm/nxp/nxp_rt118x.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -1135,6 +1135,12 @@
		};
		};

		src: reset-controller@44460000 {
		compatible = "nxp,imx-src-rev2";
		reg = <0x44460000 0xa4>;
		status = "okay";
		};

		tpm1: pwm@4310000 {
		compatible = "nxp,kinetis-tpm";
		reg = <0x4310000 0x88>;

modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

+0 −1

Original line number	Diff line number	Diff line
		@@ -282,7 +282,6 @@ endif()
		if(CONFIG_SOC_SERIES_IMXRT118X)
		set(CONFIG_MCUX_COMPONENT_driver.ele_base_api ON)
		set(CONFIG_MCUX_COMPONENT_driver.anadig_pmu_1 ON)
		set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 CONFIG_MCUX_COMPONENT_driver.src_3)
		set_variable_ifdef(CONFIG_WDT_MCUX_RTWDOG CONFIG_MCUX_COMPONENT_driver.src_3)
		endif()

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